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Freescale Semiconductor Data Sheet: Advance Information
Document Number: MPC5643L Rev. 6, 03/2011
MPC5643L
MPC5643L Microcontroller Data Sheet
MAPBGA-225 15 mm x 15 mm QFN12 ##_mm_x_##mm
SOT-343R ##_mm_x_##mm
144 LQFP (20 x 20 mm)
TBD
PKG-TBD ## mm x ## mm
257 MAPBGA (14 x 14 mm)
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1.1
Introduction
Document overview
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This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the devices. This document provides electrical specifications, pin assignments, and package diagrams for the MPC5643L series of microcontroller units (MCUs). For functional characteristics, see the MPC5643L Microcontroller Reference Manual. For use of the MPC5643Lin a fail-safe system according to safety standard IEC 61508, see the Safety Application Guide for MPC5643L. The MPC5643L MCU series is available in two silicon versions, or "cuts". These are referred to as "cut1" and "cut2" throughout this document. Functional differences between the two cuts are clearly identified with the labels "cut1" and "cut2".
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1.2
* * *
Description
Contain enhancements that improve the architecture's fit in embedded applications Include additional instruction support for digital signal processing (DSP) Integrate technologies such as an enhanced time processor unit, enhanced queued analog-to-digital converter, Controller Area Network, and an enhanced modular input-output system
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The MPC5643L series microcontrollers are system-on-chip devices that are built on Power Architecture technology and:
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.4 Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.5 Feature summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.6 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . 22 2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2 Supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.3 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2.4 Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . 72 3.3 Recommended operating conditions . . . . . . . . . . . . . . 73 3.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 74 3.5 Electromagnetic Interference (EMI) characteristics (cut1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.6 Electrostatic discharge (ESD) characteristics. . . . . . . . 77 3.7 Static latch-up (LU). . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.8 Voltage regulator electrical characteristics . . . . . . . . . . 78 3.9 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . 81 3.10 Supply current characteristics (cut2) . . . . . . . . . . . . . . 82 3.11 Temperature sensor electrical characteristics . . . . . . . 83 3.12 Main oscillator electrical characteristics . . . . . . . . . . . . 83 3.13 FMPLL electrical characteristics. . . . . . . . . . . . . . . . . . 85 3.14 16 MHz RC oscillator electrical characteristics . . . . . . 87 3.15 ADC electrical characteristics. . . . . . . . . . . . . . . . . . . . 87 3.16 Flash memory electrical characteristics . . . . . . . . . . . . 92 3.17 SWG electrical characteristics . . . . . . . . . . . . . . . . . . . 93 3.18 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 3.19 Reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.20 AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . 100 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 4.1 Package mechanical data. . . . . . . . . . . . . . . . . . . . . . 112 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . 118
This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. (c) Freescale Semiconductor, Inc., 2009-2011. All rights reserved. Preliminary--Subject to Change Without Notice
Introduction
The MPC5643L family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. It belongs to an expanding range of automotive-focused products designed to address electrical hydraulic power steering (EHPS), electric power steering (EPS) and airbag applications. The advanced and cost-efficient host processor core of the MPC5643L automotive controller family complies with the Power Architecture embedded category. It operates at speeds as high as 120 MHz and offers high-performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users' implementations.
1.3
Device comparison
Table 1. MPC5643L device summary
Feature CPU Type Architecture Execution speed DMIPS intrinsic performance SIMD (DSP + FPU) MMU Instruction set PPC Instruction set VLE Instruction cache MPU-16 regions Semaphore unit (SEMA4) Buses Core bus Internal periphery bus Crossbar Memory Master x slave ports Code/data flash Static RAM (SRAM) Modules Interrupt Controller (INTC) Periodic Interrupt Timer (PIT) System Timer Module (STM) Software Watchdog Timer (SWT) eDMA FlexRay FlexCAN LINFlexD (UART and LIN with DMA support) Clock out Fault Collection and Control Unit (FCCU) MPC5643L 2 x e200z4 (in lock-step or decoupled operation) Harvard 0-120 MHz (+2% FM) >240 MIPS Yes 16 entry Yes Yes 4 KB, EDC Yes, replicated module Yes AHB, 32-bit address, 64-bit data 32-bit address, 32-bit data Lock Step Mode: 4 x 3 Decoupled Parallel Mode: 6 x 3 1 MB, ECC, RWW 128 KB, ECC 16 interrupt levels, replicated module 1 x 4 channels 1 x 4 channels, replicated module Yes, replicated module 16 channels, replicated module 1 x 64 message buffers, dual channel 2 x 32 message buffers 2 Yes Yes
MPC5643L Microcontroller Data Sheet, Rev. 6 2 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Introduction
Table 1. MPC5643L device summary (continued)
Feature Modules (cont.) Cross Triggering Unit (CTU) eTimer FlexPWM Analog-to-Digital Converter (ADC) Sine Wave Generator (SWG) Deserial Serial Peripheral Interface (DSPI) Cyclic Redundancy Checker (CRC) unit Junction temperature sensor (TSENS) Digital I/Os Supply Device power supply Analog reference voltage Clocking Frequency-modulated phase-locked loop (FMPLL) Internal RC oscillator External crystal oscillator Debug Packages Nexus Known Good Die (KGD) LQFP MAPBGA Temperature Temperature range (junction) Ambient temperature range using external ballast transistor (LQFP) Ambient temperature range using external ballast transistor (BGA)
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MPC5643L Yes 3 x 6 channels1 2 Module 4 x (2 + 1) channels2 2 x 12-bit ADC, 16 channels per ADC (3 internal, 4 shared and 9 external) 32 point 3 x DSPI as many as 8 chip selects Yes Yes, replicated module 16 3.3 V with integrated bypassable ballast transistor External ballast transistor not needed for bare die 3.0 V - 3.6 V and 4.5 V - 5.5 V 2 16 MHz 4 - 40 MHz Level 3+ Yes 144 pins 257 MAPBGA -40 to 150 C -40 to 125 C TBD
The third eTimer is available only in the BGA package. The second FlexPWM module is available only in the BGA package.
1.4
Block diagram
Figure 1 shows a top-level block diagram of the MPC5643L device.
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 3
Introduction
PMU SWT ECSM STM INTC SEMA4 eDMA
e200z4
SPE VLE MMU I-CACHE
JTAG Nexus
e200z4
SPE VLE MMU I-CACHE
PMU SWT ECSM STM INTC SEMA4 eDMA
FlexRay RC
Crossbar Switch Memory Protection Unit ECC logic for SRAM
Crossbar Switch Memory Protection Unit ECC logic for SRAM
PBRIDGE
RC
RC
PBRIDGE
TSENS
Flash memory ECC bits + logic RC
Secondary FMPLL
SRAM ECC bits
TSENS
IRCOSC
FMPLL
SSCM
CMU
CMU
CMU
BAM
CRC FlexPWM FlexPWM LINFlexD LINFlexD FlexCAN FlexCAN eTimer eTimer eTimer DSPI DSPI DSPI CTU
WakeUp
XOSC
SIUL
FCCU
ADC
ADC
PIT SWG
MC
ADC BAM CMU CRC CTU DSPI ECC ECSM eDMA FCCU FlexCAN FMPLL INTC IRCOSC JTAG
- Analog-to-Digital Converter - Boot Assist Module - Clock Monitoring Unit - Cyclic Redundancy Check unit - Cross Triggering Unit - Serial Peripherals Interface - Error Correction Code - Error Correction Status Module - Enhanced Direct Memory Access controller - Fault Collection and Control Unit - Controller Area Network controller - Frequency Modulated Phase Locked Loop - Interrupt Controller - Internal RC Oscillator - Joint Test Action Group interface
LINFlexD MC PBRIDGE PIT PMU RC RTC SEMA4 SIUL SSCM STM SWG SWT TSENS XOSC
- LIN controller with DMA support - Mode Entry, Clock, Reset, & Power - Peripheral bridge - Periodic Interrupt Timer - Power Management Unit - Redundancy Checker - Real Time Clock - Semaphore Unit - System Integration Unit Lite - System Status and Configuration Module - System Timer Module - Sine Wave Generator - Software Watchdog Timer - Temperature Sensor - Crystal Oscillator
Figure 1. MPC5643L block diagram
MPC5643L Microcontroller Data Sheet, Rev. 6 4 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Introduction
1.5
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Feature summary
High-performance e200z4d dual core -- 32-bit Power Architecture(R) technology CPU -- Core frequency as high as 120 MHz -- Dual issue five-stage pipeline core -- Variable Length Encoding (VLE) -- Memory Management Unit (MMU) -- 4 KB instruction cache with error detection code -- Signal processing engine (SPE) Memory available -- 1 MB flash memory with ECC -- 128 KB on-chip SRAM with ECC -- Built-in RWW capabilities for EEPROM emulation SIL3/ASILD innovative safety concept: LockStep mode and Fail-safe protection -- Sphere of replication (SoR) for key components (such as CPU core, eDMA, crossbar switch) -- Fault collection and control unit (FCCU) -- Redundancy control and checker unit (RCCU) on outputs of the SoR connected to FCCU -- Boot-time Built-In Self-Test for Memory (MBIST) and Logic (LBIST) triggered by hardware -- Boot-time Built-In Self-Test for ADC and flash memory triggered by software -- Replicated safety enhanced watchdog -- Replicated junction temperature sensor -- Non-maskable interrupt (NMI) -- 16-region memory protection unit (MPU) -- Clock monitoring units (CMU) -- Power management unit (PMU) -- Cyclic redundancy check (CRC) unit Decoupled Parallel mode for high-performance use of replicated cores Nexus Class 3+ interface Interrupts -- Replicated 16-priority controller -- Replicated 16-channel eDMA controller GPIOs individually programmable as input, output or special function Three 6-channel general-purpose eTimer units 2 FlexPWM units -- Four 16-bit channels per module Communications interfaces -- 2 LINFlexD channels -- 3 DSPI channels with automatic chip select generation -- 2 FlexCAN interfaces (2.0B Active) with 32 message objects -- FlexRay module (V2.1 Rev. A) with 2 channels, 64 message buffers and data rates up to 10 Mbit/s Two 12-bit analog-to-digital converters (ADCs) -- 16 input channels -- Programmable cross triggering unit (CTU) to synchronize ADCs conversion with timer and PWM Sine wave generator (D/A with low pass filter) On-chip CAN/UART bootstrap loader
MPC5643L Microcontroller Data Sheet, Rev. 6
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Preliminary--Subject to Change Without Notice
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Introduction
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Single 3.0 V to 3.6 V voltage supply Ambient temperature range -40 C to 125 C Junction temperature range -40 C to 150 C
1.6
1.6.1
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Feature details
High-performance e200z4d core
2 independent execution units, both supporting fixed-point and floating-point operations Dual issue 32-bit Power Architecture technology compliant -- 5-stage pipeline (IF, DEC, EX1, EX2, WB) -- In-order execution and instruction retirement Full support for Power Architecture instruction set and Variable Length Encoding (VLE) -- Mix of classic 32-bit and 16-bit instruction allowed -- Optimization of code size possible Thirty-two 64-bit general purpose registers (GPRs) Harvard bus (32-bit address, 64-bit data) -- I-Bus interface capable of one outstanding transaction plus one piped with no wait-on-data return -- D-Bus interface capable of two transactions outstanding to fill AHB pipe I-cache and I-cache controller -- 4 KB, 256-bit cache line (programmable for 2- or 4-way) No data cache 16-entry MMU 8-entry branch table buffer Branch look-ahead instruction buffer to accelerate branching Dedicated branch address calculator 3 cycles worst case for missed branch Load/store unit -- Fully pipelined -- Single-cycle load latency -- Big- and little-endian modes supported -- Misaligned access support -- Single stall cycle on load to use Single-cycle throughput (2-cycle latency) integer 32 x 32 multiplication 4 - 14 cycles integer 32 x 32 division (average division on various benchmark of nine cycles) Single precision floating-point unit -- 1 cycle throughput (2-cycle latency) floating-point 32 x 32 multiplication -- Target 9 cycles (worst case acceptable is 12 cycles) throughput floating-point 32 x 32 division -- Special square root and min/max function implemented Signal processing support: APU-SPE 1.1 -- Support for vectorized mode: as many as two floating-point instructions per clock Vectored interrupt support Reservation instruction to support read-modify-write constructs
MPC5643L Microcontroller Data Sheet, Rev. 6
The e200z4d Power Architecture(R) core provides the following features:
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Introduction
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Extensive system development and tracing support via Nexus debug port
1.6.2
Crossbar switch (XBAR)
The XBAR multi-port crossbar switch supports simultaneous connections between four master ports and three slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width. The crossbar allows four concurrent transactions to occur from any master port to any slave port, although one of those transfers must be an instruction fetch from internal flash memory. If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher priority master and grants it ownership of the slave port. All other masters requesting that slave port are stalled until the higher priority master completes its transactions. The crossbar provides the following features: * 4 masters and 3 slaves supported per each replicated crossbar -- Masters allocation for each crossbar: e200z4d core with two independent bus interface units (BIU) for I and D access (2 masters), one eDMA, one FlexRay -- Slaves allocation for each crossbar: a redundant flash-memory controller with 2 slave ports to guarantee maximum flexibility to handle Instruction and Data array, one redundant SRAM controller with 1 slave port each and 1 redundant peripheral bus bridge 32-bit address bus and 64-bit data bus Programmable arbitration priority -- Requesting masters can be treated with equal priority and are granted access to a slave port in round-robin method, based upon the ID of the last master to be granted access or a priority order can be assigned by software at application run time Temporary dynamic priority elevation of masters
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The XBAR is replicated for each processing channel.
1.6.3
Memory Protection Unit (MPU)
The Memory Protection Unit splits the physical memory into 16 different regions. Each master (eDMA, FlexRay, CPU) can be assigned different access rights to each region. * * 16-region MPU with concurrent checks against each master access 32-byte granularity for protected address region
The memory protection unit is replicated for each processing channel.
1.6.4
Enhanced Direct Memory Access (eDMA)
The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data movements via 16 programmable channels, with minimal intervention from the host processor. The hardware microarchitecture includes a DMA engine which performs source and destination address calculations, and the actual data movement operations, along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation is used to minimize the overall block size. The eDMA module provides the following features: * * * * * * 16 channels supporting 8-, 16-, and 32-bit value single or block transfers Support variable sized queues and circular buffered queue Source and destination address registers independently configured to post-increment or stay constant Support major and minor loop offset Support minor and major loop done signals DMA task initiated either by hardware requestor or by software
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 7
Introduction
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Each DMA task can optionally generate an interrupt at completion and retirement of the task Signal to indicate closure of last minor loop Transfer control descriptors mapped inside the SRAM
The eDMA controller is replicated for each processing channel.
1.6.5
On-chip flash memory with ECC
This device includes programmable, non-volatile flash memory. The non-volatile memory (NVM) can be used for instruction storage or data storage, or both. The flash memory module interfaces with the system bus through a dedicated flash memory array controller. It supports a 64-bit data bus width at the system bus port, and a 128-bit read data interface to flash memory. The module contains four 128-bit prefetch buffers. Prefetch buffer hits allow no-wait responses. Buffer misses incur a 3 wait state response at 120 MHz. The flash memory module provides the following features * * * * * 1 MB of flash memory in unique multi-partitioned hard macro Sectorization: 16 KB + 2 x 48 KB + 16 KB + 2 x 64 KB + 2 x 128 KB + 2 x 256 KB EEPROM emulation (in software) within same module but on different partition 16 KB test sector and 16 KB shadow sector for test, censorship device and user option bits Wait states: -- 3 wait states at 120 MHz -- 2 wait states at 80 MHz -- 1 wait state at 60 MHz Flash memory line 128-bit wide with 8-bit ECC on 64-bit word (total 144 bits) Accessed via a 64-bit wide bus for write and a 128-bit wide array for read operations 1-bit error correction, 2-bit error detection
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1.6.6
On-chip SRAM with ECC
The MPC5643L SRAM provides a general-purpose single port memory. ECC handling is done on a 32-bit boundary for data and it is extended to the address to have the highest possible diagnostic coverage including the array internal address decoder. The SRAM module provides the following features: * * * * System SRAM: 128 KB ECC on 32-bit word (syndrome of 7 bits) -- ECC covers SRAM bus address 1-bit error correction, 2-bit error detection Wait states: -- 1 wait state at 120 MHz -- 0 wait states at 80 MHz and 60 MHz
1.6.7
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Platform flash memory controller
Single AHB port interface supports a 64-bit data bus. All AHB aligned and unaligned reads within the 32-bit container are supported. Only aligned word writes are supported. Array interfaces support a 128-bit read data bus and a 64-bit write data bus for each bank. Code flash (bank0) interface provides configurable read buffering and page prefetch support.
MPC5643L Microcontroller Data Sheet, Rev. 6
The following list summarizes the key features of the flash memory controller:
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Preliminary--Subject to Change Without Notice
Freescale Semiconductor
Introduction
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-- Four page-read buffers (each 128 bits wide) and a prefetch controller support speculative reading and optimized flash access. Single-cycle read responses (0 AHB data-phase wait states) for hits in the buffers. The buffers implement a least-recently-used replacement algorithm to maximize performance. Data flash (bank1) interface includes a 128-bit register to temporarily hold a single flash page. This logic supports single-cycle read responses (0 AHB data-phase wait states) for accesses that hit in the holding register. -- No prefetch support is provided for this bank. Programmable response for read-while-write sequences including support for stall-while-write, optional stall notification interrupt, optional flash operation abort , and optional abort notification interrupt. Separate and independent configurable access timing (on a per bank basis) to support use across a wide range of platforms and frequencies. Support of address-based read access timing for emulation of other memory types. Support for reporting of single- and multi-bit error events. Typical operating configuration loaded into programming model by system reset.
The platform flash controller is replicated for each processor.
1.6.8
Platform Static RAM Controller (SRAMC)
The SRAMC module is the platform SRAM array controller, with integrated error detection and correction. The main features of the SRAMC provide connectivity for the following interfaces: * * * * * * XBAR Slave Port (64-bit data path) ECSM (ECC Error Reporting, error injection and configuration) SRAM array ECC encoding (32-bit boundary for data and complete address bus) ECC decoding (32-bit boundary and entire address) Address translation from the AHB protocol on the XBAR to the SRAM array
The following functions are implemented:
The platform SRAM controller is replicated for each processor.
1.6.9
Memory subsystem access time
Every memory access the CPU performs requires at least one system clock cycle for the data phase of the access. Slower memories or peripherals may require additional data phase wait states. Additional data phase wait states may also occur if the slave being accessed is not parked on the requesting master in the crossbar. Table 2 shows the number of additional data phase wait states required for a range of memory accesses. Table 2. Platform memory access time summary
AHB transfer e200z4d instruction fetch e200z4d instruction fetch e200z4d data read e200z4d data write Data phase wait states 0 3 0-1 0 Description Flash memory prefetch buffer hit (page hit) Flash memory prefetch buffer miss (based on 4-cycle random flash array access time) SRAM read SRAM 32-bit write
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 9
Introduction
Table 2. Platform memory access time summary (continued)
AHB transfer e200z4d data write e200z4d data write e200z4d flash memory read e200z4d flash memory read Data phase wait states 0 0-2 0 3 Description SRAM 64-bit write (executed as 2 x 32-bit writes) SRAM 8-,16-bit write (Read-modify-Write for ECC) Flash memory prefetch buffer hit (page hit) Flash memory prefetch buffer miss (at 120 MHz; includes 1 cycle of program flash memory controller arbitration)
1.6.10
Error Correction Status Module (ECSM)
The ECSM on this device manages the ECC configuration and reporting for the platform memories (flash memory and SRAM). It does not implement the actual ECC calculation. A detected error (double error for flash memory or SRAM) is also reported to the FCCU. The following errors and indications are reported into the ECSM dedicated registers: * * * * ECC error status and configuration for flash memory and SRAM ECC error reporting for flash memory ECC error reporting for SRAM ECC error injection for SRAM
1.6.11
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Peripheral bridge (PBRIDGE)
The PBRIDGE implements the following features: Duplicated periphery Master access right per peripheral (per master: read access enable; write access enable) Checker applied on PBRIDGE output toward periphery Byte endianess swap capability
1.6.12
Interrupt Controller (INTC)
The INTC provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time systems. For high-priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of interrupt request, the priority of each interrupt request is software configurable. The INTC supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource can not preempt each other. The INTC provides the following features: * * * * Duplicated periphery Unique 9-bit vector per interrupt source 16 priority levels with fixed hardware arbitration within priority levels for each interrupt source Priority elevation for shared resource
The INTC is replicated for each processor.
MPC5643L Microcontroller Data Sheet, Rev. 6 10 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Introduction
1.6.13
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System clocks and clock generation
The following list summarizes the system clock and clock generation on this device: Lock status continuously monitored by lock detect circuitry Loss-of-clock (LOC) detection for reference and feedback clocks On-chip loop filter (for improved electromagnetic interference performance and fewer external components required) Programmable output clock divider of system clock (1, 2, 4, 8) FlexPWM module and as many as three eTimer modules running on an auxiliary clock independent from system clock (with max frequency 120 MHz) On-chip crystal oscillator with automatic level control Dedicated internal 16 MHz internal RC oscillator for rapid start-up -- Supports automated frequency trimming by hardware during device startup and by user application Auxiliary clock domain for motor control periphery (FlexPWM, eTimer, CTU, ADC, and SWG)
1.6.14
Frequency-Modulated Phase-Locked Loop (FMPLL)
Each device has two FMPLLs. Each FMPLL allows the user to generate high speed system clocks starting from a minimum reference of 4 MHz input clock. Further, the FMPLL supports programmable frequency modulation of the system clock. The FMPLL multiplication factor, output clock divider ratio are all software configurable. The FMPLLs have the following major features: * * * Input frequency: 4-40 MHz continuous range (limited by the crystal oscillator) Voltage controlled oscillator (VCO) range: 256-512 MHz Frequency modulation via software control to reduce and control emission peaks -- Modulation depth 2% if centered or 0% to -4% if downshifted via software control register -- Modulation frequency: triangular modulation with 25 kHz nominal rate Option to switch modulation on and off via software interface Reduced frequency divider (RFD) for reduced frequency operation without re-lock 3 modes of operation -- Bypass mode -- Normal FMPLL mode with crystal reference (default) -- Normal FMPLL mode with external reference Lock monitor circuitry with lock status Loss-of-lock detection for reference and feedback clocks Self-clocked mode (SCM) operation On-chip loop filter Auxiliary FMPLL -- Used for FlexRay due to precise symbol rate requirement by the protocol -- Used for motor control periphery and connected IP (A/D digital interface CTU) to allow independent frequencies of operation for PWM and timers and jitter-free control -- Option to enable/disable modulation to avoid protocol violation on jitter and/or potential unadjusted error in electric motor control loop -- Allows to run motor control periphery at different (precisely lower, equal or higher as required) frequency than the system to ensure higher resolution
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MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11
Introduction
1.6.15
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Main oscillator
The main oscillator provides these features: Input frequency range 4-40 MHz Crystal input mode External reference clock (3.3 V) input mode FMPLL reference
1.6.16
Internal Reference Clock (RC) oscillator
The architecture uses constant current charging of a capacitor. The voltage at the capacitor is compared to the stable bandgap reference voltage. The RC oscillator is the device safe clock. The RC oscillator provides these features: * * * * Nominal frequency 16 MHz 5% variation over voltage and temperature after process trim Clock output of the RC oscillator serves as system clock source in case loss of lock or loss of clock is detected by the FMPLL RC oscillator is used as the default system clock during startup and can be used as back-up input source of FMPLL(s) in case XOSC fails
1.6.17
Clock, reset, power, mode and test control modules (MC_CGM, MC_RGM, MC_PCU, and MC_ME)
These modules provide the following: * * * * Clock gating and clock distribution control Halt, stop mode control Flexible configurable system and auxiliary clock dividers Various execution modes -- HALT and STOP mode as reduced activity low power mode -- Reset, Idle, Test, Safe -- Various RUN modes with software selectable powered modules -- No stand-by mode implemented (no internal switchable power domains)
1.6.18
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Periodic Interrupt Timer Module (PIT)
The PIT module implements the following features: 4 general purpose interrupt timers 32-bit counter resolution Can be used for software tick or DMA trigger operation
1.6.19
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System Timer Module (STM)
The STM implements the following features: Up-counter with 4 output compare registers OS task protection and hardware tick implementation per AUTOSAR1 requirement
1.Automotive Open System Architecture
MPC5643L Microcontroller Data Sheet, Rev. 6 12 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Introduction
The STM is replicated for each processor.
1.6.20
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Software Watchdog Timer (SWT)
This module implements the following features: Fault tolerant output Safe internal RC oscillator as reference clock Windowed watchdog Program flow control monitor with 16-bit pseudorandom key generation Allows a high level of safety (SIL3 monitor)
The SWT module is replicated for each processor.
1.6.21
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Fault Collection and Control Unit (FCCU)
The FCCU module has the following features: Redundant collection of hardware checker results Redundant collection of error information and latch of faults from critical modules on the device Collection of self-test results Configurable and graded fault control -- Internal reactions (no internal reaction, IRQ, Functional Reset, Destructive Reset, or Safe mode entered) -- External reaction (failure is reported to the external/surrounding system via configurable output pins)
1.6.22
System Integration Unit Lite (SIUL)
The SIUL controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO), internal peripheral multiplexing, and system reset operation. The reset configuration block contains the external pin boot configuration logic. The pad configuration block controls the static electrical characteristics of I/O pins. The GPIO block provides uniform and discrete input/output control of the I/O pins of the MCU. The SIU provides the following features: * Centralized pad control on a per-pin basis -- Pin function selection -- Configurable weak pull-up/down -- Configurable slew rate control (slow/medium/fast) -- Hysteresis on GPIO pins -- Configurable automatic safe mode pad control Input filtering for external interrupts
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1.6.23
Non-Maskable Interrupt (NMI)
The non-maskable interrupt with de-glitching filter supports high-priority core exceptions.
1.6.24
Boot Assist Module (BAM)
The BAM is a block of read-only memory with hard-coded content. The BAM program is executed only if serial booting mode is selected via boot configuration pins.
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 13
Introduction
The BAM provides the following features: * * * * Enables booting via serial mode (FlexCAN or LINFlex-UART) Supports programmable 64-bit password protection for serial boot mode Supports serial bootloading of either Power Architecture code (default) or Freescale VLE code Automatic switch to serial boot mode if internal flash memory is blank or invalid
1.6.25
* * * * *
System Status and Configuration Module (SSCM)
The SSCM on this device features the following: System configuration and status Debug port status and debug port enable Multiple boot code starting locations out of reset through implementation of search for valid Reset Configuration Half Word Sets up the MMU to allow user boot code to execute as either Power Architecture code (default) or as Freescale VLE code out of flash memory Triggering of device self-tests during reset phase of device boot
1.6.26
FlexCAN
The FlexCAN module is a communication controller implementing the CAN protocol according to Bosch Specification version 2.0B. The CAN protocol was designed to be used primarily as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness and required bandwidth. The FlexCAN module provides the following features: * Full implementation of the CAN protocol specification, version 2.0B -- Standard data and remote frames -- Extended data and remote frames -- 0 to 8 bytes data length -- Programmable bit rate as fast as 1Mbit/s 32 message buffers of 0 to 8 bytes data length Each message buffer configurable as receive or transmit buffer, all supporting standard and extended messages Programmable loop-back mode supporting self-test operation 3 programmable mask registers Programmable transmit-first scheme: lowest ID or lowest buffer number Time stamp based on 16-bit free-running timer Global network time, synchronized by a specific message Maskable interrupts Independent of the transmission medium (an external transceiver is assumed) High immunity to EMI Short latency time due to an arbitration scheme for high-priority messages Transmit features -- Supports configuration of multiple mailboxes to form message queues of scalable depth -- Arbitration scheme according to message ID or message buffer number -- Internal arbitration to guarantee no inner or outer priority inversion -- Transmit abort procedure and notification Receive features
* * * * * * * * * * * *
*
MPC5643L Microcontroller Data Sheet, Rev. 6 14 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Introduction
*
-- Individual programmable filters for each mailbox -- 8 mailboxes configurable as a 6-entry receive FIFO -- 8 programmable acceptance filters for receive FIFO Programmable clock source -- System clock -- Direct oscillator clock to avoid FMPLL jitter
1.6.27
* * * * * * * * *
FlexRay
The FlexRay module provides the following features: Full implementation of FlexRay Protocol Specification 2.1 Rev. A 64 configurable message buffers can be handled Dual channel or single channel mode of operation, each as fast as 10 Mbit/s data rate Message buffers configurable as transmit or receive Message buffer size configurable Message filtering for all message buffers based on Frame ID, cycle count, and message ID Programmable acceptance filters for receive FIFO Message buffer header, status, and payload data stored in system memory (SRAM) Internal FlexRay memories have error detection and correction
1.6.28
* * * *
Serial communication interface module (LINFlexD)
The LINFlexD module (LINFlex with DMA support) on this device features the following: Supports LIN Master mode, LIN Slave mode and UART mode LIN state machine compliant to LIN1.3, 2.0, and 2.1 specifications Manages LIN frame transmission and reception without CPU intervention LIN features -- Autonomous LIN frame handling -- Message buffer to store as many as 8 data bytes -- Supports messages as long as 64 bytes -- Detection and flagging of LIN errors (Sync field, delimiter, ID parity, bit framing, checksum and Time-out errors) -- Classic or extended checksum calculation -- Configurable break duration of up to 36-bit times -- Programmable baud rate prescalers (13-bit mantissa, 4-bit fractional) -- Diagnostic features (Loop back, LIN bus stuck dominant detection) -- Interrupt driven operation with 16 interrupt sources LIN slave mode features -- Autonomous LIN header handling -- Autonomous LIN response handling UART mode -- Full-duplex operation -- Standard non return-to-zero (NRZ) mark/space format -- Data buffers with 4-byte receive, 4-byte transmit -- Configurable word length (8-bit, 9-bit, or 16-bit words) -- Configurable parity scheme: none, odd, even, always 0 -- Speed as fast as 2 Mbit/s
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 15
*
*
Introduction
*
-- Error detection and flagging (Parity, Noise and Framing errors) -- Interrupt driven operation with four interrupt sources -- Separate transmitter and receiver CPU interrupt sources -- 16-bit programmable baud-rate modulus counter and 16-bit fractional -- 2 receiver wake-up methods Support for DMA enabled transfers
1.6.29
Deserial Serial Peripheral Interface (DSPI)
The DSPI modules provide a synchronous serial interface for communication between the MPC5643L and external devices. A DSPI module provides these features: * * * * * * * * * * * * * Full duplex, synchronous transfers Master or slave operation Programmable master bit rates Programmable clock polarity and phase End-of-transmission interrupt flag Programmable transfer baud rate Programmable data frames from 4 to 16 bits As many as 8 chip select lines available, depending on package and pin multiplexing 4 clock and transfer attributes registers Chip select strobe available as alternate function on one of the chip select pins for de-glitching FIFOs for buffering as many as 5 transfers on the transmit and receive side Queueing operation possible through use of the eDMA General purpose I/O functionality on pins when not used for SPI
1.6.30
FlexPWM
The pulse width modulator module (FlexPWM) contains four PWM channels, each of which is configured to control a single half-bridge power stage. Two modules are included on 257 MAPBGA devices; on the 144 LQFP package, only one module is present. Additionally, four fault input channels are provided per FlexPWM module. This PWM is capable of controlling most motor types, including: * * * * * * * * * * * * AC induction motors (ACIM) Permanent Magnet AC motors (PMAC) Brushless (BLDC) and brush DC motors (BDC) Switched (SRM) and variable reluctance motors (VRM) Stepper motors 16 bits of resolution for center, edge aligned, and asymmetrical PWMs Maximum operating frequency as high as 120 MHz -- Clock source not modulated and independent from system clock (generated via secondary FMPLL) Fine granularity control for enhanced resolution of the PWM period PWM outputs can operate as complementary pairs or independent channels Ability to accept signed numbers for PWM generation Independent control of both edges of each PWM output Synchronization to external hardware or other PWM supported
A FlexPWM module implements the following features:
MPC5643L Microcontroller Data Sheet, Rev. 6 16 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Introduction
*
* * * * * * * * * * * * *
*
Double buffered PWM registers -- Integral reload rates from 1 to 16 -- Half cycle reload capability Multiple ADC trigger events can be generated per PWM cycle via hardware Fault inputs can be assigned to control multiple PWM outputs Programmable filters for fault inputs Independently programmable PWM output polarity Independent top and bottom deadtime insertion Each complementary pair can operate with its own PWM frequency and deadtime values Individual software control for each PWM output All outputs can be forced to a value simultaneously PWMX pin can optionally output a third signal from each channel Channels not used for PWM generation can be used for buffered output compare functions Channels not used for PWM generation can be used for input capture functions Enhanced dual edge capture functionality Option to supply the source for each complementary PWM signal pair from any of the following: -- External digital pin -- Internal timer channel -- External ADC input, taking into account values set in ADC high- and low-limit registers DMA support
1.6.31
eTimer module
The MPC5643L provides three eTimer modules on the 257 MAPBGA device, and two eTimer modules on the 144 LQFP package. Six 16-bit general purpose up/down timer/counters per module are implemented with the following features: * * Maximum clock frequency of 120 MHz Individual channel capability -- Input capture trigger -- Output compare -- Double buffer (to capture rising edge and falling edge) -- Separate prescaler for each counter -- Selectable clock source -- 0-100% pulse measurement -- Rotation direction flag (Quad decoder mode) Maximum count rate -- Equals peripheral clock divided by 2 for external event counting -- Equals peripheral clock for internal clock counting Cascadeable counters Programmable count modulo Quadrature decode capabilities Counters can share available input pins Count once or repeatedly Preloadable counters Pins available as GPIO when timer functionality not in use DMA support
*
* * * * * * * *
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17
Introduction
1.6.32
* *
Sine Wave Generator (SWG)
A digital-to-analog converter is available to generate a sine wave based on 32 stored values for external devices (ex: resolver). Frequency range from 1 kHz to 50 kHz Sine wave amplitude from 0.47 V to 2.26 V
1.6.33
Analog part: *
Analog-to-Digital Converter module (ADC)
The ADC module features include: 2 on-chip ADCs -- 12-bit resolution SAR architecture -- Same digital interface as in the MPC5604P family -- A/D Channels: 9 external, 3 internal and 4 shared with other A/D (total 16 channels) -- One channel dedicated to each T-sensor to enable temperature reading during application -- Separated reference for each ADC -- Shared analog supply voltage for both ADCs -- One sample and hold unit per ADC -- Adjustable sampling and conversion time 4 analog watchdogs comparing ADC results against predefined levels (low, high, range) before results are stored in the appropriate ADC result location 2 modes of operation: Motor Control Mode or Regular Mode Regular mode features -- Register based interface with the CPU: one result register per channel -- ADC state machine managing three request flows: regular command, hardware injected command, software injected command -- Selectable priority between software and hardware injected commands -- 4 analog watchdogs comparing ADC results against predefined levels (low, high, range) -- DMA compatible interface CTU mode features -- Triggered mode only -- 4 independent result queues (1 16 entries, 2 8 entries, 1 4 entries) -- Result alignment circuitry (left justified; right justified) -- 32-bit read mode allows to have channel ID on one of the 16-bit parts -- DMA compatible interfaces Built-in self-test features triggered by software
Digital part: * * *
*
*
1.6.34
Cross Triggering Unit (CTU)
The ADC cross triggering unit allows automatic generation of ADC conversion requests on user selected conditions without CPU load during the PWM period and with minimized CPU load for dynamic configuration. The CTU implements the following features: * * * Cross triggering between ADC, FlexPWM, eTimer, and external pins Double buffered trigger generation unit with as many as 8 independent triggers generated from external triggers Maximum operating frequency less than or equal to 120 MHz
MPC5643L Microcontroller Data Sheet, Rev. 6 18 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Introduction
* * * * * * * *
Trigger generation unit configurable in sequential mode or in triggered mode Trigger delay unit to compensate the delay of external low pass filter Double buffered global trigger unit allowing eTimer synchronization and/or ADC command generation Double buffered ADC command list pointers to minimize ADC-trigger unit update Double buffered ADC conversion command list with as many as 24 ADC commands Each trigger capable of generating consecutive commands ADC conversion command allows control of ADC channel from each ADC, single or synchronous sampling, independent result queue selection DMA support with safety features
1.6.35
Cyclic Redundancy Checker (CRC) Unit
The CRC module is a configurable multiple data flow unit to compute CRC signatures on data written to its input register. The CRC unit has the following features: * * 3 sets of registers to allow 3 concurrent contexts with possibly different CRC computations, each with a selectable polynomial and seed Computes 16- or 32-bit wide CRC on the fly (single-cycle computation) and stores result in internal register. The following standard CRC polynomials are implemented: -- x8 + x4 + x3 + x2 + 1 [8-bit CRC] (supported on cut2 only) -- x16 + x12 + x5 + 1 [16-bit CRC-CCITT] -- x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1 [32-bit CRC-ethernet(32)] Key engine to be coupled with communication periphery where CRC application is added to allow implementation of safe communication protocol Offloads core from cycle-consuming CRC and helps checking configuration signature for safe start-up or periodic procedures CRC unit connected as peripheral bus on internal peripheral bus DMA support
* * * *
1.6.36
* *
Redundancy Control and Checker Unit (RCCU)
The RCCU checks all outputs of the sphere of replication (addresses, data, control signals). It has the following features: Duplicated module to guarantee highest possible diagnostic coverage (check of checker) Multiple times replicated IPs are used as checkers on the SoR outputs
1.6.37
Junction temperature sensor
The junction temperature sensor provides a value via an ADC channel that can be used by software to calculate the device junction temperature. The key parameters of the junction temperature sensor include: * * Nominal temperature range from -40 to 150 C Software temperature alarm via analog ADC comparator possible
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 19
Introduction
1.6.38
Nexus Port Controller (NPC)
The NPC module provides real-time development support capabilities for this device in compliance with the IEEE-ISTO 5001-2008 standard. This development support is supplied for MCUs without requiring external address and data pins for internal visibility. The NPC block interfaces to the host processor and internal buses to provide development support as per the IEEE-ISTO 5001-2008 Class 3+, including selected features from Class 4 standard. The development support provided includes program trace, data trace, watchpoint trace, ownership trace, run-time access to the MCUs internal memory map and access to the Power Architecture internal registers during halt. The Nexus interface also supports a JTAG only mode using only the JTAG pins. The following features are implemented: * * * * * * * * Full and reduced port modes MCKO (message clock out) pin 4 or 12 MDO (message data out) pins1 2 MSEO (message start/end out) pins EVTO (event out) pin -- Auxiliary input port EVTI (event in) pin 5-pin JTAG port (JCOMP, TDI, TDO, TMS, and TCK) -- Supports JTAG mode Host processor (e200) development support features -- Data trace via data write messaging (DWM) and data read messaging (DRM). This allows the development tool to trace reads or writes, or both, to selected internal memory resources. -- Ownership trace via ownership trace messaging (OTM). OTM facilitates ownership trace by providing visibility of which process ID or operating system task is activated. An ownership trace message is transmitted when a new process/task is activated, allowing development tools to trace ownership flow. -- Program trace via branch trace messaging (BTM). Branch trace messaging displays program flow discontinuities (direct branches, indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires between the discontinuities. Thus, static code may be traced. -- Watchpoint messaging (WPM) via the auxiliary port -- Watchpoint trigger enable of program and/or data trace messaging -- Data tracing of instruction fetches via private opcodes
1.6.39
IEEE 1149.1 JTAG Controller (JTAGC)
The JTAGC block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. All data input to and output from the JTAGC block is communicated in serial format. The JTAGC block is compliant with the IEEE standard. The JTAG controller provides the following features: * IEEE Test Access Port (TAP) interface with 5 pins: -- TDI -- TMS -- TCK -- TDO
1. 4 MDO pins on 144 LQFP package, 12 MDO pins on 257 MAPBGA package.
MPC5643L Microcontroller Data Sheet, Rev. 6 20 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Introduction
* *
* *
-- JCOMP Selectable modes of operation include JTAGC/debug or normal system operation 5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions: -- BYPASS -- IDCODE -- EXTEST -- SAMPLE -- SAMPLE/PRELOAD 3 test data registers: a bypass register, a boundary scan register, and a device identification register. The size of the boundary scan register is parameterized to support a variety of boundary scan chain lengths. TAP controller state machine that controls the operation of the data registers, instruction register and associated circuitry
1.6.40
* *
Voltage regulator / Power Management Unit (PMU)
The on-chip voltage regulator module provides the following features: Single external rail required Single high supply required: nominal 3.3 V both for packaged and Known Good Die option -- Packaged option requires external ballast transistor due to reduced dissipation capacity at high temperature but can use embedded transistor if power dissipation is maintained within package dissipation capacity (lower frequency of operation) -- Known Good Die option uses embedded ballast transistor as dissipation capacity is increased to reduce system cost All I/Os are at same voltage as external supply (3.3 V nominal) Duplicated Low-Voltage Detectors (LVD) to guarantee proper operation at all stages (reset, configuration, normal operation) and, to maximize safety coverage, one LVD can be tested while the other operates (on-line self-testing feature)
* *
1.6.41
* * * *
Built-In Self-Test (BIST) capability
This device includes the following protection against latent faults: Boot-time Memory Built-In Self-Test (MBIST) Boot-time scan-based Logic Built-In Self-Test (LBIST) Run-time ADC Built-In Self-Test (BIST) Run-time Built-In Self Test of LVDs
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 21
Package pinouts and signal descriptions
2
2.1
Package pinouts and signal descriptions
Package pinouts
Figure 2 shows the MPC5643L in the 144 LQFP package.
A[15] A[14] C[6] FCCU_F[1] D[2] F[3] B[6] VSS_LV_COR A[13] VDD_LV_COR A[9] F[0] VSS_LV_COR VDD_LV_COR VDD_HV_REG_2 D[4] D[3] VSS_HV_IO VDD_HV_IO D[0] C[15] JCOMP A[12] E[15] A[11] E[14] A[10] E[13] B[3] F[14] B[2] F[15] F[13] C[10] B[1] B[0] NMI A[6] D[1] F[4] F[5] VDD_HV_IO VSS_HV_IO F[6] MDO0 A[7] C[4] A[8] C[5] A[5] C[7] VDD_HV_REG_0 VSS_LV_COR VDD_LV_COR F[7] F[8] VDD_HV_IO VSS_HV_IO F[9] F[10] F[11] D[9] VDD_HV_OSC VSS_HV_OSC XTAL EXTAL RESET D[8] D[5] D[6] VSS_LV_PLL0_PLL1 VDD_LV_PLL0_PLL1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
144 LQFP package
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
A[4] VPP_TEST F[12] D[14] G[3] C[14] G[2] C[13] G[4] D[12] G[6] VDD_HV_FLA VSS_HV_FLA VDD_HV_REG_1 VSS_LV_COR VDD_LV_COR A[3] VDD_HV_IO VSS_HV_IO B[4] TCK TMS B[5] G[5] A[2] G[7] C[12] G[8] C[11] G[9] D[11] G[10] D[10] G[11] A[1] A[0]
Figure 2. MPC5643L 144 LQFP pinout (top view) Figure 3 shows the MPC5643L in the 257 MAPBGA package.
22
D[7] FCCU_F[0] VDD_LV_COR VSS_LV_COR C[1] E[4] B[7] E[5] C[2] E[6] B[8] E[7] E[2] VDD_HV_ADR0 VSS_HV_ADR0 B[9] B[10] B[11] B[12] VDD_HV_ADR1 VSS_HV_ADR1 VDD_HV_ADV VSS_HV_ADV B[13] E[9] B[15] E[10] B[14] E[11] C[0] E[12] E[0] BCTRL VDD_LV_COR VSS_LV_COR VDD_HV_PMU
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
MPC5643L Microcontroller Data Sheet, Rev. 6 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Package pinouts and signal descriptions
1 A
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
VSS VSS VDD_HV F[5]
VSS VSS NC1
VDD_HV B[6]
H[2]
H[0]
G[14]
D[3]
C[15]
VDD_HV VSS I[0]
A[12]
H[10]
H[14]
A[10]
B[2]
C[10]
VSS VDD_HV A[4]
VSS VSS F[12]
B
A[14]
F[3]
A[9]
D[4]
D[0]
H[12]
E[15]
E[14]
B[3]
F[13]
B[0]
C
VSS A[15]
FCCU_ F[1] C[6]
D[2]
A[13]
VDD_HV VDD_HV F[0] VDD_HV
JCOMP
H[11]
I[1]
F[14]
B[1]
VSS VPP
_TEST
D
F[4]
VSS
VDD_LV
VSS
NC
A[11]
E[13]
F[15]
VDD_HV NC
D[14]
G[3]
E
MDO0
F[6]
D[1]
NMI
C[14]
G[2]
I[3]
F
H[1]
G[12]
A[7]
A[8]
VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV
NC
C[13]
I[2]
G[4]
G
H[3]
VDD_HV VSS G[15]
C[5]
A[6]
D[12]
H[13]
H[9]
G[6]
H
G[13]
C[4]
A[5]
VSS
VDD_HV VDD_HV VSS H[7]
H[6]
J
F[7]
VDD_HV VDD_HV See note2 D[9] C[7]
VDD_LV VDD_HV NC H[8]
H[15]
K
F[9]
F[8]
A[3]
L
F[10]
F[11]
NC
NC
TCK
H[4]
B[4]
M
VDD_HV VDD_HV XTAL VSS RESET FCCU _F[0] VDD_HV VSS
2
D[8]
NC VSS_LV_
PLL
VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV
C[11]
B[5]
TMS
H[5]
N
D[5]
NC
C[12]
A[2]
G[5]
P
VSS EXTAL
D[6]
VDD_LV_
PLL
VDD_LV B[7]
VSS E[6]
B[8] VREFP_
HV_AD0
NC
VSS VREFP_
HV_AD1
VDD_HV B[13]
B[14]
VDD_LV C[0]
VSS BCTRL
VDD_HV A[1]
G[10]
G[8]
G[7]
R
VSS NC
D[7]
B[10]
B[15]
VSS D[10]
D[11]
G[9]
T
VSS VSS
1
C[1]
E[5]
E[7]
VREFN_
HV_AD0
B[11]
VREFN_
HV_AD1
E[9]
E[10]
E[12]
E[0]
A[0]
VDD_HV VSS
16
VSS VSS
17
U
NC
3
E[4]
4
C[2]
5
E[2]
6
B[9]
7
B[12]
8
VDD_HV
9
VSS
10
E[11]
11
NC
12
NC
13
VDD_HV
14
G[11]
15
1 2
NC = Not connected (the pin is physically not connected to anything on the device) Pin K3 is NC on cut1 and RDY on cut2.
Figure 3. MPC5643L 257 MAPBGA pinout (top view) Table 3 and Table 4 provide the pin function summaries for the 144-pin and 257-pin packages, respectively, listing all the signals multiplexed to each pin.
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 23
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary
Pin # 1 2 Port/function NMI A[6] SIUL DSPI_1 SIUL 3 D[1] SIUL eTimer_1 CTU_0 FlexRay 4 F[4] SIUL NPC 5 F[5] SIUL NPC 6 7 8 VDD_HV_IO VSS_HV_IO F[6] SIUL NPC 9 10 MDO0 A[7] SIUL DSPI_1 SIUL 11 C[4] SIUL DSPI_0 FlexPWM_0 SSCM SIUL 12 A[8] SIUL DSPI_1 SIUL 13 C[5] SIUL DSPI_0 SSCM FlexPWM_0 SIUL Peripheral Output function -- GPIO[6] SCK -- GPIO[49] ETC[2] EXT_TGR -- GPIO[84] MDO[3] GPIO[85] MDO[2] -- -- GPIO[86] MDO[1] -- GPIO[7] SOUT -- GPIO[36] CS0 X[1] DEBUG[4] -- GPIO[8] -- -- GPIO[37] SCK DEBUG[5] -- -- GPIO[7] -- EIRQ[7] GPIO[36] CS0 X[1] -- EIRQ[22] GPIO[8] SIN EIRQ[8] GPIO[37] SCK -- FAULT[3] EIRQ[23] GPIO[86] -- GPIO[6] SCK EIRQ[6] GPIO[49] ETC[2] -- CA_RX GPIO[84] -- GPIO[85] -- Input function
MPC5643L Microcontroller Data Sheet, Rev. 6 24 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin # 14 Port/function A[5] Peripheral SIUL DSPI_1 eTimer_1 DSPI_0 SIUL 15 C[7] SIUL FlexPWM_0 SSCM DSPI_0 16 17 18 19 VDD_HV_REG_0 VSS_LV_COR VDD_LV_COR F[7] SIUL NPC 20 F[8] SIUL NPC 21 22 23 VDD_HV_IO VSS_HV_IO F[9] SIUL NPC 24 F[10] SIUL NPC 25 F[11] SIUL NPC 26 D[9] SIUL FlexPWM_0 LINFlexD_1 27 28 29 30 31 VDD_HV_OSC VSS_HV_OSC XTALIN XTALOUT RESET Output function GPIO[5] CS0 ETC[5] CS7 -- GPIO[39] A[1] DEBUG[7] -- -- -- -- GPIO[87] MCKO GPIO[88] MSEO[1] -- -- GPIO[89] MSEO[0] GPIO[90] EVTO GPIO[91] EVTI GPIO[57] X[0] TXD -- -- -- -- -- GPIO[89] -- GPIO[90] -- GPIO[91] -- GPIO[57] X[0] -- GPIO[87] -- GPIO[88] -- Input function GPIO[5] CS0 ETC[5] -- EIRQ[5] GPIO[39] A[1] -- SIN
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 25
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin # 32 Port/function D[8] Peripheral SIUL DSPI_1 eTimer_1 DSPI_0 FlexPWM_0 33 D[5] SIUL DSPI_0 FlexPWM_0 34 D[6] SIUL DSPI_0 FlexPWM_0 FlexPWM_0 35 36 37 VSS_LV_PLL0_PLL1 VDD_LV_PLL0_PLL1 D[7] SIUL DSPI_1 DSPI_0 SWG 38 39 40 41 FCCU_F[0] VDD_LV_COR VSS_LV_COR C[1] SIUL ADC_0 42 E[4] SIUL ADC_0 43 B[7] SIUL LINFlexD_0 ADC_0 44 E[5] SIUL ADC_0 45 C[2] SIUL ADC_0 46 E[6] SIUL ADC_0 FCCU Output function GPIO[56] CS2 ETC[4] CS5 -- GPIO[53] CS3 -- GPIO[54] CS2 X[3] -- -- -- GPIO[55] CS3 CS4 analog output F[0] -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- GPIO[33] AN[2] GPIO[68] AN[7] GPIO[23] RXD AN[0] GPIO[69] AN[8] GPIO[34] AN[3] GPIO[70] AN[4] GPIO[55] -- -- -- F[0] Input function GPIO[56] -- ETC[4] -- FAULT[3] GPIO[53] -- FAULT[2] GPIO[54] -- X[3] FAULT[1]
MPC5643L Microcontroller Data Sheet, Rev. 6 26 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin # 47 Port/function B[8] Peripheral SIUL eTimer_0 ADC_0 48 E[7] SIUL ADC_0 49 E[2] SIUL ADC_0 50 51 52 VDD_HV_ADR0 VSS_HV_ADR0 B[9] SIUL ADC_0 ADC_1 53 B[10] SIUL ADC_0 ADC_1 54 B[11] SIUL ADC_0 ADC_1 55 B[12] SIUL ADC_0 ADC_1 56 57 58 59 60 VDD_HV_ADR1 VSS_HV_ADR1 VDD_HV_ADV VSS_HV_ADV B[13] SIUL LINFlexD_1 ADC_1 61 E[9] SIUL ADC_1 62 B[15] SIUL SIUL ADC_1 63 E[10] SIUL ADC_1 Output function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- GPIO[29] RXD AN[0] GPIO[73] AN[7] GPIO[31] EIRQ[20] AN[2] GPIO[74] AN[8] GPIO[25] AN[11] GPIO[26] AN[12] GPIO[27] AN[13] GPIO[28] AN[14] Input function GPIO[24] ETC[5] AN[1] GPIO[71] AN[6] GPIO[66] AN[5]
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 27
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin # 64 Port/function B[14] Peripheral SIUL eTimer_0 SIUL ADC_1 65 E[11] SIUL ADC_1 66 C[0] SIUL ADC_1 67 E[12] SIUL ADC_1 68 E[0] SIUL ADC_1 69 70 71 72 73 BCTRL VDD_LV_COR VSS_LV_COR VDD_HV_PMU A[0] SIUL eTimer_0 DSPI_2 SIUL 74 A[1] SIUL eTimer_0 DSPI_2 SIUL 75 G[11] SIUL FlexRay FlexPWM_0 76 D[10] SIUL FlexPWM_0 eTimer_0 77 G[10] SIUL FlexRay DSPI_2 FlexPWM_0 Output function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- GPIO[0] ETC[0] SCK -- GPIO[1] ETC[1] SOUT -- GPIO[107] DBG3 -- GPIO[58] A[0] -- GPIO[106] DBG2 CS3 -- GPIO[0] ETC[0] SCK EIRQ[0] GPIO[1] ETC[1] -- EIRQ[1] GPIO[107] -- FAULT[3] GPIO[58] A[0] ETC[0] GPIO[106] -- -- FAULT[2] Input function GPIO[30] ETC[4] EIRQ[19] AN[1] GPIO[75] AN[4] GPIO[32] AN[3] GPIO[76] AN[6] GPIO[64] AN[5]
MPC5643L Microcontroller Data Sheet, Rev. 6 28 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin # 78 Port/function D[11] Peripheral SIUL FlexPWM_0 eTimer_0 79 G[9] SIUL FlexRay DSPI_1 FlexPWM_0 SIUL 80 C[11] SIUL eTimer_0 DSPI_2 81 G[8] SIUL FlexRay DSPI_0 FlexPWM_0 SIUL 82 C[12] SIUL eTimer_0 DSPI_2 83 G[7] SIUL FlexPWM_0 84 A[2] SIUL eTimer_0 FlexPWM_0 DSPI_2 MC_RGM SIUL 85 G[5] SIUL FlexPWM_0 DSPI_2 86 B[5] SIUL JTAGC 87 88 TMS TCK Output function GPIO[59] B[0] -- GPIO[105] DBG1 CS1 -- -- GPIO[43] ETC[4] CS2 GPIO[104] DBG0 CS1 -- -- GPIO[44] ETC[5] CS3 GPIO[103] B[3] GPIO[2] ETC[2] A[3] -- -- -- GPIO[101] X[3] CS3 GPIO[21] -- -- -- Input function GPIO[59] B[0] ETC[1] GPIO[105] -- -- FAULT[1] EIRQ[29] GPIO[43] ETC[4] -- GPIO[104] -- -- FAULT[0] EIRQ[21] GPIO[44] ETC[5] -- GPIO[103] B[3] GPIO[2] ETC[2] A[3] SIN ABS[0] EIRQ[2] GPIO[101] X[3] -- GPIO[21] TDI
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 29
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin # 89 Port/function B[4] Peripheral SIUL JTAGC 90 91 92 VSS_HV_IO VDD_HV_IO A[3] SIUL eTimer_0 DSPI_2 FlexPWM_0 MC_RGM SIUL 93 94 95 96 97 98 VDD_LV_COR VSS_LV_COR VDD_HV_REG_1 VSS_HV_FLA VDD_HV_FLA G[6] SIUL FlexPWM_0 99 D[12] SIUL FlexPWM_0 LINFlexD_1 100 G[4] SIUL FlexPWM_0 eTimer_0 101 C[13] SIUL eTimer_1 CTU_0 FlexPWM_0 102 G[2] SIUL FlexPWM_0 DSPI_1 103 C[14] SIUL eTimer_1 CTU_0 Output function GPIO[20] TDO -- -- GPIO[3] ETC[3] CS0 B[3] -- -- -- -- -- -- -- GPIO[102] A[3] GPIO[60] X[1] -- GPIO[100] B[2] -- GPIO[45] ETC[1] -- -- GPIO[98] X[2] CS1 GPIO[46] ETC[2] EXT_TGR GPIO[102] A[3] GPIO[60] X[1] RXD GPIO[100] B[2] ETC[5] GPIO[45] ETC[1] EXT_IN EXT_SYNC GPIO[98] X[2] -- GPIO[46] ETC[2] -- GPIO[3] ETC[3] CS0 B[3] ABS[2] EIRQ[3] Input function GPIO[20] --
MPC5643L Microcontroller Data Sheet, Rev. 6 30 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin # 104 Port/function G[3] Peripheral SIUL FlexPWM_0 eTimer_0 105 D[14] SIUL FlexPWM_0 eTimer_0 106 F[12] SIUL eTimer_1 SIUL 107 108 VPP_TEST A[4]
1
Output function GPIO[99] A[2] -- GPIO[62] B[1] -- GPIO[92] ETC[3] -- --
Input function GPIO[99] A[2] ETC[4] GPIO[62] B[1] ETC[3] GPIO[92] ETC[3] EIRQ[30]
SIUL eTimer_1 DSPI_2 eTimer_0 MC_RGM SIUL
GPIO[4] ETC[0] CS1 ETC[4] -- -- GPIO[16] TXD ETC[2] DEBUG[0] -- GPIO[17] ETC[3] DEBUG[1] -- -- -- GPIO[42] CS2 A[3] -- GPIO[93] ETC[4] --
GPIO[4] ETC[0] -- ETC[4] FAB EIRQ[4] GPIO[16] -- ETC[2] -- EIRQ[15] GPIO[17] ETC[3] -- RXD RXD EIRQ[16] GPIO[42] -- A[3] FAULT[1] GPIO[93] ETC[4] EIRQ[31]
109
B[0]
SIUL FlexCAN_0 eTimer_1 SSCM SIUL
110
B[1]
SIUL eTimer_1 SSCM FlexCAN_0 FlexCAN_1 SIUL
111
C[10]
SIUL DSPI_2 FlexPWM_0 FlexPWM_0
112
F[13]
SIUL eTimer_1 SIUL
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 31
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin # 113 Port/function F[15] Peripheral SIUL LINFlexD_1 114 B[2] SIUL LINFlexD_0 SSCM SIUL 115 F[14] SIUL LINFlexD_1 116 B[3] SIUL SSCM LINFlexD_0 117 E[13] SIUL eTimer_0 DSPI_2 SIUL 118 A[10] SIUL DSPI_2 FlexPWM_0 FlexPWM_0 SIUL 119 E[14] SIUL eTimer_1 SIUL 120 A[11] SIUL DSPI_2 FlexPWM_0 FlexPWM_0 SIUL 121 E[15] SIUL DSPI_0 SIUL Output function GPIO[95] -- GPIO[18] TXD DEBUG[2] -- GPIO[94] TXD GPIO[19] DEBUG[3] -- GPIO[77] ETC[5] CS3 -- GPIO[10] CS0 B[0] X[2] -- GPIO[78] ETC[5] -- GPIO[11] SCK A[0] A[2] -- GPIO[79] CS1 -- Input function GPIO[95] RXD GPIO[18] -- -- EIRQ[17] GPIO[94] -- GPIO[19] -- RXD GPIO[77] ETC[5] -- EIRQ[25] GPIO[10] CS0 B[0] X[2] EIRQ[9] GPIO[78] ETC[5] EIRQ[26] GPIO[11] SCK A[0] A[2] EIRQ[10] GPIO[79] -- EIRQ[27]
MPC5643L Microcontroller Data Sheet, Rev. 6 32 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin # 122 Port/function A[12] Peripheral SIUL DSPI_2 FlexPWM_0 FlexPWM_0 SIUL 123 124 JCOMP C[15] -- SIUL FlexRay eTimer_1 FlexPWM_0 CTU_0 FlexPWM_0 125 D[0] SIUL FlexRay eTimer_1 FlexPWM_0 126 127 128 VDD_HV_IO VSS_HV_IO D[3] SIUL FlexRay eTimer_1 FlexPWM_0 129 D[4] SIUL FlexRay eTimer_1 FlexPWM_0 130 131 132 133 VDD_HV_REG_2 VDD_LV_COR VSS_LV_COR F[0] SIUL FlexPWM_0 eTimer_0 SIUL Output function GPIO[12] SOUT A[2] B[2] -- -- GPIO[47] CA_TR_EN ETC[0] A[1] -- -- GPIO[48] CA_TX ETC[1] B[1] -- -- GPIO[51] CB_TX ETC[4] A[3] GPIO[52] CB_TR_EN ETC[5] B[3] -- -- -- GPIO[80] A[1] -- -- GPIO[80] A[1] ETC[2] EIRQ[28] GPIO[51] -- ETC[4] A[3] GPIO[52] -- ETC[5] B[3] Input function GPIO[12] -- A[2] B[2] EIRQ[11] JCOMP GPIO[47] -- ETC[0] A[1] EXT_IN EXT_SYNC GPIO[48] -- ETC[1] B[1]
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 33
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin # 134 Port/function A[9] Peripheral SIUL DSPI_2 FlexPWM_0 FlexPWM_0 135 136 VDD_LV_COR A[13] SIUL FlexPWM_0 DSPI_2 FlexPWM_0 SIUL 137 138 VSS_LV_COR B[6] SIUL MC_CGM DSPI_2 SIUL 139 F[3] SIUL DSPI_0 140 D[2] SIUL eTimer_1 FlexPWM_0 FlexRay 141 142 FCCU_F[1] C[6] FCCU SIUL DSPI_0 FlexPWM_0 SSCM SIUL 143 A[14] SIUL FlexCAN_1 eTimer_1 SIUL Output function GPIO[9] CS1 B[3] -- -- GPIO[13] B[2] -- -- -- -- GPIO[22] clk_out CS2 -- GPIO[83] CS6 GPIO[50] ETC[3] X[3] -- F[1] GPIO[38] SOUT B[1] DEBUG[6] -- GPIO[14] TXD ETC[4] -- GPIO[22] -- -- EIRQ[18] GPIO[83] -- GPIO[50] ETC[3] X[3] CB_RX F[1] GPIO[38] -- B[1] -- EIRQ[24] GPIO[14] -- ETC[4] EIRQ[13] GPIO[13] B[2] SIN FAULT[0] EIRQ[12] Input function GPIO[9] -- B[3] FAULT[0]
MPC5643L Microcontroller Data Sheet, Rev. 6 34 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin # 144 Port/function A[15] Peripheral SIUL eTimer_1 FlexCAN_1 FlexCAN_0 SIUL
1
Output function GPIO[15] ETC[5] -- -- --
Input function GPIO[15] ETC[5] RXD RXD EIRQ[14]
VPP_TEST should always be tied to ground (VSS) for normal operations.
Table 4. 257 MAPBGA pin function summary
Pin # A1 A2 A3 A4 Port/function VSS_HV_IO_RING VSS_HV_IO_RING VDD_HV_IO_RING H[2] SIUL NPC A5 H[0] SIUL NPC A6 G[14] SIUL NPC A7 D[3] SIUL FlexRay eTimer_1 FlexPWM_0 A8 C[15] SIUL FlexRay eTimer_1 FlexPWM_0 CTU_0 FlexPWM_0 A9 A10 VDD_HV_IO_RING A[12] SIUL DSPI_2 FlexPWM_0 FlexPWM_0 SIUL Peripheral Output function -- -- -- GPIO[114] MDO[5] GPIO[112] MDO[7] GPIO[110] MDO[9] GPIO[51] CB_TX ETC[4] A[3] GPIO[47] CA_TR_EN ETC[0] A[1] -- -- -- GPIO[12] SOUT A[2] B[2] -- GPIO[12] -- A[2] B[2] EIRQ[11] GPIO[114] -- GPIO[112] -- GPIO[110] -- GPIO[51] -- ETC[4] A[3] GPIO[47] -- ETC[0] A[1] EXT_IN EXT_SYNC Input function
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 35
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin # A11 Port/function H[10] Peripheral SIUL FlexPWM_1 eTimer_2 A12 H[14] SIUL FlexPWM_1 eTimer_2 A13 A[10] SIUL DSPI_2 FlexPWM_0 FlexPWM_0 SIUL A14 B[2] SIUL LINFlexD_0 SSCM SIUL A15 C[10] SIUL DSPI_2 FlexPWM_0 FlexPWM_0 A16 A17 B1 B2 B3 VSS_HV_IO_RING VSS_HV_IO_RING VSS_HV_IO_RING VSS_HV_IO_RING B[6] SIUL MC_CGM DSPI_2 SIUL B4 A[14] SIUL FlexCAN_1 eTimer_1 SIUL B5 F[3] SIUL DSPI_0 Output function GPIO[122] X[2] ETC[2] GPIO[126] A[3] ETC[4] GPIO[10] CS0 B[0] X[2] -- GPIO[18] TXD DEBUG[2] -- GPIO[42] CS2 A[3] -- -- -- -- -- GPIO[22] clk_out CS2 -- GPIO[14] TXD ETC[4] -- GPIO[83] CS6 GPIO[22] -- -- EIRQ[18] GPIO[14] -- ETC[4] EIRQ[13] GPIO[83] -- Input function GPIO[122] X[2] ETC[2] GPIO[126] A[3] ETC[4] GPIO[10] CS0 B[0] X[2] EIRQ[9] GPIO[18] -- -- EIRQ[17] GPIO[42] -- A[3] FAULT[1]
MPC5643L Microcontroller Data Sheet, Rev. 6 36 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin # B6 Port/function A[9] Peripheral SIUL DSPI_2 FlexPWM_0 FlexPWM_0 B7 D[4] SIUL FlexRay eTimer_1 FlexPWM_0 B8 D[0] SIUL FlexRay eTimer_1 FlexPWM_0 B9 B10 VSS_HV_IO_RING H[12] SIUL FlexPWM_1 B11 E[15] SIUL DSPI_0 SIUL B12 E[14] SIUL eTimer_1 SIUL B13 B[3] SIUL SSCM LINFlexD_0 B14 F[13] SIUL eTimer_1 SIUL B15 B[0] SIUL FlexCAN_0 eTimer_1 SSCM SIUL B16 B17 C1 VDD_HV_IO_RING VSS_HV_IO_RING VDD_HV_IO_RING Output function GPIO[9] CS1 B[3] -- GPIO[52] CB_TR_EN ETC[5] B[3] GPIO[48] CA_TX ETC[1] B[1] -- GPIO[124] B[2] GPIO[79] CS1 -- GPIO[78] ETC[5] -- GPIO[19] DEBUG[3] -- GPIO[93] ETC[4] -- GPIO[16] TXD ETC[2] DEBUG[0] -- -- -- -- GPIO[124] B[2] GPIO[79] -- EIRQ[27] GPIO[78] ETC[5] EIRQ[26] GPIO[19] -- RXD GPIO[93] ETC[4] EIRQ[31] GPIO[16] -- ETC[2] -- EIRQ[15] Input function GPIO[9] -- B[3] FAULT[0] GPIO[52] -- ETC[5] B[3] GPIO[48] -- ETC[1] B[1]
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin # C2 C3 C4 C5 Port/function Not connected VSS_HV_IO_RING FCCU_F[1] D[2] FCCU SIUL eTimer_1 FlexPWM_0 FlexRay C6 A[13] SIUL FlexPWM_0 DSPI_2 FlexPWM_0 SIUL C7 C8 C9 VDD_HV_REG_2 VDD_HV_REG_2 I[0] SIUL eTimer_2 DSPI_0 FlexPWM_1 C10 C11 JCOMP H[11] -- SIUL FlexPWM_1 C12 I[1] SIUL eTimer_2 DSPI_0 FlexPWM_1 C13 F[14] SIUL LINFlexD_1 C14 B[1] SIUL eTimer_1 SSCM FlexCAN_0 FlexCAN_1 SIUL C15 VSS_HV_IO_RING Peripheral Output function -- -- F[1] GPIO[50] ETC[3] X[3] -- GPIO[13] B[2] -- -- -- -- -- GPIO[128] ETC[0] CS4 -- -- GPIO[123] A[2] GPIO[129] ETC[1] CS5 -- GPIO[94] TXD GPIO[17] ETC[3] DEBUG[1] -- -- -- -- GPIO[128] ETC[0] -- FAULT[0] JCOMP GPIO[123] A[2] GPIO[129] ETC[1] -- FAULT[1] GPIO[94] -- GPIO[17] ETC[3] -- RXD RXD EIRQ[16] F[1] GPIO[50] ETC[3] X[3] CB_RX GPIO[13] B[2] SIN FAULT[0] EIRQ[12] Input function
MPC5643L Microcontroller Data Sheet, Rev. 6 38 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin # C16 Port/function A[4] Peripheral SIUL eTimer_1 DSPI_2 eTimer_0 MC_RGM SIUL C17 F[12] SIUL eTimer_1 SIUL D1 F[5] SIUL NPC D2 F[4] SIUL NPC D3 A[15] SIUL eTimer_1 FlexCAN_1 FlexCAN_0 SIUL D4 C[6] SIUL DSPI_0 FlexPWM_0 SSCM SIUL D5 D6 D7 VSS_LV_CORE_RING VDD_LV_CORE_RING F[0] SIUL FlexPWM_0 eTimer_0 SIUL D8 D9 D10 VDD_HV_IO_RING VSS_HV_IO_RING Not connected Output function GPIO[4] ETC[0] CS1 ETC[4] -- -- GPIO[92] ETC[3] -- GPIO[85] MDO[2] GPIO[84] MDO[3] GPIO[15] ETC[5] -- -- -- GPIO[38] SOUT B[1] DEBUG[6] -- -- -- GPIO[80] A[1] -- -- -- -- -- GPIO[80] A[1] ETC[2] EIRQ[28] Input function GPIO[4] ETC[0] -- ETC[4] FAB EIRQ[4] GPIO[92] ETC[3] EIRQ[30] GPIO[85] -- GPIO[84] -- GPIO[15] ETC[5] RXD RXD EIRQ[14] GPIO[38] -- B[1] -- EIRQ[24]
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 39
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin # D11 Port/function A[11] Peripheral SIUL DSPI_2 FlexPWM_0 FlexPWM_0 SIUL D12 E[13] SIUL eTimer_0 DSPI_2 SIUL D13 F[15] SIUL LINFlexD_1 D14 D15 D16 VDD_HV_IO_RING VPP_TEST D[14]
1
Output function GPIO[11] SCK A[0] A[2] -- GPIO[77] ETC[5] CS3 -- GPIO[95] -- -- --
Input function GPIO[11] SCK A[0] A[2] EIRQ[10] GPIO[77] ETC[5] -- EIRQ[25] GPIO[95] RXD
SIUL FlexPWM_0 eTimer_0
GPIO[62] B[1] -- GPIO[99] A[2] -- --
GPIO[62] B[1] ETC[3] GPIO[99] A[2] ETC[4]
D17
G[3]
SIUL FlexPWM_0 eTimer_0
E1 E2
MDO0 F[6] SIUL NPC
GPIO[86] MDO[1] GPIO[49] ETC[2] EXT_TGR -- -- --
GPIO[86] -- GPIO[49] ETC[2] -- CA_RX
E3
D[1]
SIUL eTimer_1 CTU_0 FlexRay
E4 E14 E15
NMI Not connected C[14] SIUL eTimer_1 CTU_0
GPIO[46] ETC[2] EXT_TGR GPIO[98] X[2] CS1
GPIO[46] ETC[2] -- GPIO[98] X[2] --
E16
G[2]
SIUL FlexPWM_0 DSPI_1
MPC5643L Microcontroller Data Sheet, Rev. 6 40 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin # E17 Port/function I[3] Peripheral SIUL eTimer_2 DSPI_0 CTU_0 FlexPWM_1 F1 H[1] SIUL NPC F2 G[12] SIUL NPC F3 A[7] SIUL DSPI_1 SIUL F4 A[8] SIUL DSPI_1 SIUL F6 F7 F8 F9 F10 F11 F12 F14 F15 VDD_LV_CORE_RING VDD_LV_CORE_RING VDD_LV_CORE_RING VDD_LV_CORE_RING VDD_LV_CORE_RING VDD_LV_CORE_RING VDD_LV_CORE_RING Not connected C[13] SIUL eTimer_1 CTU_0 FlexPWM_0 F16 I[2] SIUL eTimer_2 DSPI_0 FlexPWM_1 F17 G[4] SIUL FlexPWM_0 eTimer_0 Output function GPIO[131] ETC[3] CS7 EXT_TGR -- GPIO[113] MDO[6] GPIO[108] MDO[11] GPIO[7] SOUT -- GPIO[8] -- -- -- -- -- -- -- -- -- -- GPIO[45] ETC[1] -- -- GPIO[130] ETC[2] CS6 -- GPIO[100] B[2] -- GPIO[45] ETC[1] EXT_IN EXT_SYNC GPIO[130] ETC[2] -- FAULT[2] GPIO[100] B[2] ETC[5] Input function GPIO[131] ETC[3] -- -- FAULT[3] GPIO[113] -- GPIO[108] -- GPIO[7] -- EIRQ[7] GPIO[8] SIN EIRQ[8]
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 41
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin # G1 Port/function H[3] Peripheral SIUL NPC G2 G3 VDD_HV_IO_RING C[5] SIUL DSPI_0 SSCM FlexPWM_0 SIUL G4 A[6] SIUL DSPI_1 SIUL G6 G7 G8 G9 G10 G11 G12 G14 VDD_LV_CORE_RING VSS_LV_CORE_RING VSS_LV_CORE_RING VSS_LV_CORE_RING VSS_LV_CORE_RING VSS_LV_CORE_RING VDD_LV_CORE_RING D[12] SIUL FlexPWM_0 LINFlexD_1 G15 H[13] SIUL FlexPWM_1 eTimer_2 G16 H[9] SIUL FlexPWM_1 DSPI_0 G17 G[6] SIUL FlexPWM_0 H1 G[13] SIUL NPC H2 VSS_HV_IO_RING Output function GPIO[115] MDO[4] -- GPIO[37] SCK DEBUG[5] -- -- GPIO[6] SCK -- -- -- -- -- -- -- -- GPIO[60] X[1] -- GPIO[125] X[3] ETC[3] GPIO[121] B[1] CS7 GPIO[102] A[3] GPIO[109] MDO[10] -- GPIO[60] X[1] RXD GPIO[125] X[3] ETC[3] GPIO[121] B[1] -- GPIO[102] A[3] GPIO[109] -- GPIO[37] SCK -- FAULT[3] EIRQ[23] GPIO[6] SCK EIRQ[6] Input function GPIO[115] --
MPC5643L Microcontroller Data Sheet, Rev. 6 42 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin # H3 Port/function C[4] Peripheral SIUL DSPI_0 FlexPWM_0 SSCM SIUL H4 A[5] SIUL DSPI_1 eTimer_1 DSPI_0 SIUL H6 H7 H8 H9 H10 H11 H12 H14 H15 H16 H17 VDD_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VDD_LV VSS_LV VDD_HV_REG_1 VDD_HV_FLA H[6] SIUL FlexPWM_1 DSPI_0 J1 F[7] SIUL NPC J2 G[15] SIUL NPC J3 J4 J6 J7 J8 J9 J10 J11 VDD_HV_REG_0 VDD_HV_REG_0 VDD_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV Output function GPIO[36] CS0 X[1] DEBUG[4] -- GPIO[5] CS0 ETC[5] CS7 -- -- -- -- -- -- -- -- -- -- -- GPIO[118] B[0] CS5 GPIO[87] MCKO GPIO[111] MDO[8] -- -- -- -- -- -- -- -- GPIO[118] B[0] -- GPIO[87] -- GPIO[111] -- Input function GPIO[36] CS0 X[1] -- EIRQ[22] GPIO[5] CS0 ETC[5] -- EIRQ[5]
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 43
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin # J12 J14 J15 J16 J17 Port/function VDD_LV VDD_LV VDD_HV_REG_1 VSS_HV_FLA H[15] SIUL FlexPWM_1 eTimer_2 K1 F[9] SIUL NPC K2 F[8] SIUL NPC K3 (cut1) K3 (cut2) K4 Not connected RDY NPC SIUL C[7] SIUL FlexPWM_0 SSCM DSPI_0 K6 K7 K8 K9 K10 K11 K12 K14 K15 VDD_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VDD_LV Not connected H[8] SIUL FlexPWM_1 DSPI_0 K16 H[7] SIUL FlexPWM_1 eTimer_2 Peripheral Output function -- -- -- -- GPIO[127] B[3] ETC[5] GPIO[89] MSEO[0] GPIO[88] MSEO[1] -- RDY GPIO[132] GPIO[39] A[1] DEBUG[7] -- -- -- -- -- -- -- -- -- GPIO[120] A[1] CS6 GPIO[119] X[1] ETC[1] GPIO[120] A[1] -- GPIO[119] X[1] ETC[1] -- GPIO[132] GPIO[39] A[1] -- SIN GPIO[127] B[3] ETC[5] GPIO[89] -- GPIO[88] -- Input function
MPC5643L Microcontroller Data Sheet, Rev. 6 44 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin # K17 Port/function A[3] Peripheral SIUL eTimer_0 DSPI_2 FlexPWM_0 MC_RGM SIUL L1 F[10] SIUL NPC L2 F[11] SIUL NPC L3 D[9] SIUL FlexPWM_0 LINFlexD_1 L4 L6 L7 L8 L9 L10 L11 L12 L14 L15 L16 Not connected VDD_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VDD_LV Not connected TCK H[4] SIUL FlexPWM_1 eTimer_2 L17 B[4] SIUL JTAGC M1 M2 M3 VDD_HV_OSC VDD_HV_IO_RING D[8] SIUL DSPI_1 eTimer_1 DSPI_0 FlexPWM_0 Output function GPIO[3] ETC[3] CS0 B[3] -- -- GPIO[90] EVTO GPIO[91] EVTI GPIO[57] X[0] TXD -- -- -- -- -- -- -- -- -- -- GPIO[116] X[0] ETC[0] GPIO[20] TDO -- -- GPIO[56] CS2 ETC[4] CS5 -- GPIO[56] -- ETC[4] -- FAULT[3] GPIO[116] X[0] ETC[0] GPIO[20] -- Input function GPIO[3] ETC[3] CS0 B[3] ABS[2] EIRQ[3] GPIO[90] -- GPIO[91] -- GPIO[57] X[0] --
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 45
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin # M4 M6 M7 M8 M9 M10 M11 M12 M14 Port/function Not connected VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV C[11] SIUL eTimer_0 DSPI_2 M15 B[5] SIUL JTAGC M16 M17 TMS H[5] SIUL FlexPWM_1 DSPI_0 N1 N2 N3 XTALIN VSS_HV_IO_RING D[5] SIUL DSPI_0 FlexPWM_0 N4 N14 N15 VSS_LV_PLL0_PLL1 Not connected C[12] SIUL eTimer_0 DSPI_2 N16 A[2] SIUL eTimer_0 FlexPWM_0 DSPI_2 MC_RGM SIUL Peripheral Output function -- -- -- -- -- -- -- -- GPIO[43] ETC[4] CS2 GPIO[21] -- -- GPIO[117] A[0] CS4 -- -- GPIO[53] CS3 -- -- -- GPIO[44] ETC[5] CS3 GPIO[2] ETC[2] A[3] -- -- -- GPIO[44] ETC[5] -- GPIO[2] ETC[2] A[3] SIN ABS[0] EIRQ[2] GPIO[53] -- FAULT[2] GPIO[117] A[0] -- GPIO[43] ETC[4] -- GPIO[21] TDI Input function
MPC5643L Microcontroller Data Sheet, Rev. 6 46 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin # N17 Port/function G[5] Peripheral SIUL FlexPWM_0 DSPI_2 P1 P2 P3 VSS_HV_OSC RESET D[6] SIUL DSPI_0 FlexPWM_0 FlexPWM_0 P4 P5 P6 P7 VDD_LV_PLL0_PLL1 VDD_LV_CORE_RING VSS_LV_CORE_RING B[8] SIUL eTimer_0 ADC_0 P8 P9 P10 P11 Not connected VSS_HV_IO_RING VDD_HV_IO_RING B[14] SIUL eTimer_0 SIUL ADC_1 P12 P13 P14 P15 VDD_LV_CORE_RING VSS_LV_CORE_RING VDD_HV_IO_RING G[10] SIUL FlexRay DSPI_2 FlexPWM_0 P16 G[8] SIUL FlexRay DSPI_0 FlexPWM_0 SIUL Output function GPIO[101] X[3] CS3 -- -- GPIO[54] CS2 X[3] -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- GPIO[106] DBG2 CS3 -- GPIO[104] DBG0 CS1 -- -- GPIO[106] -- -- FAULT[2] GPIO[104] -- -- FAULT[0] EIRQ[21] GPIO[30] ETC[4] EIRQ[19] AN[1] GPIO[24] ETC[5] AN[1] GPIO[54] -- X[3] FAULT[1] Input function GPIO[101] X[3] --
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 47
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin # P17 Port/function G[7] Peripheral SIUL FlexPWM_0 R1 R2 R3 R4 XTALOUT FCCU_F[0] VSS_HV_IO_RING D[7] SIUL DSPI_1 DSPI_0 SWG R5 B[7] SIUL LINFlexD_0 ADC_0 R6 E[6] SIUL ADC_0 R7 R8 VDD_HV_ADR0 B[10] SIUL ADC_0 ADC_1 R9 R10 VDD_HV_ADR1 B[13] SIUL LINFlexD_1 ADC_1 R11 B[15] SIUL SIUL ADC_1 R12 C[0] SIUL ADC_1 R13 R14 BCTRL A[1] SIUL eTimer_0 DSPI_2 SIUL R15 VSS_HV_IO_RING FCCU Output function GPIO[103] B[3] -- F[0] -- GPIO[55] CS3 CS4 analog output -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- GPIO[1] ETC[1] SOUT -- -- GPIO[1] ETC[1] -- EIRQ[1] GPIO[29] RXD AN[0] GPIO[31] EIRQ[20] AN[2] GPIO[32] AN[3] GPIO[26] AN[12] GPIO[55] -- -- -- GPIO[23] RXD AN[0] GPIO[70] AN[4] F[0] Input function GPIO[103] B[3]
MPC5643L Microcontroller Data Sheet, Rev. 6 48 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin # R16 Port/function D[11] Peripheral SIUL FlexPWM_0 eTimer_0 R17 G[9] SIUL FlexRay DSPI_1 FlexPWM_0 SIUL T1 T2 T3 T4 VSS_HV_IO_RING VDD_HV_IO_RING Not connected C[1] SIUL ADC_0 T5 E[5] SIUL ADC_0 T6 E[7] SIUL ADC_0 T7 T8 VSS_HV_ADR0 B[11] SIUL ADC_0 ADC_1 T9 T10 VSS_HV_ADR1 E[9] SIUL ADC_1 T11 E[10] SIUL ADC_1 T12 E[12] SIUL ADC_1 T13 E[0] SIUL ADC_1 T14 A[0] SIUL eTimer_0 DSPI_2 SIUL Output function GPIO[59] B[0] -- GPIO[105] DBG1 CS1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- GPIO[0] ETC[0] SCK -- GPIO[73] AN[7] GPIO[74] AN[8] GPIO[76] AN[6] GPIO[64] AN[5] GPIO[0] ETC[0] SCK EIRQ[0] GPIO[27] AN[13] GPIO[33] AN[2] GPIO[69] AN[8] GPIO[71] AN[6] Input function GPIO[59] B[0] ETC[1] GPIO[105] -- -- FAULT[1] EIRQ[29]
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 49
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin # T15 Port/function D[10] Peripheral SIUL FlexPWM_0 eTimer_0 T16 T17 U1 U2 U3 U4 VDD_HV_IO_RING VSS_HV_IO_RING VSS_HV_IO_RING VSS_HV_IO_RING Not connected E[4] SIUL ADC_0 U5 C[2] SIUL ADC_0 U6 E[2] SIUL ADC_0 U7 B[9] SIUL ADC_0 ADC_1 U8 B[12] SIUL ADC_0 ADC_1 U9 U10 U11 VDD_HV_ADV VSS_HV_ADV E[11] SIUL ADC_1 U12 U13 U14 U15 Not connected Not connected VDD_HV_PMU G[11] SIUL FlexRay FlexPWM_0 U16 U17
1
Output function GPIO[58] A[0] -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- GPIO[107] DBG3 -- -- --
Input function GPIO[58] A[0] ETC[0]
GPIO[68] AN[7] GPIO[34] AN[3] GPIO[66] AN[5] GPIO[25] AN[11] GPIO[28] AN[14]
GPIO[75] AN[4]
GPIO[107] -- FAULT[3]
VSS_HV_IO_RING VSS_HV_IO_RING
VPP_TEST should always be tied to ground (VSS) for normal operations.
MPC5643L Microcontroller Data Sheet, Rev. 6 50 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Package pinouts and signal descriptions
2.2
Supply pins
Table 5. Supply pins
Supply Symbol Description VREG control and power supply pins BCTRL VDD_LV_COR VSS_LV_COR VDD_HV_PMU Voltage regulator external NPN ballast base control pin Core logic supply Core regulator ground Voltage regulator supply ADC_0/ADC_1 reference voltage and ADC supply VDD_HV_ADR0 VSS_HV_ADR0 VDD_HV_ADR1 VSS_HV_ADR1 VDD_HV_ADV VSS_HV_ADV ADC_0 high reference voltage ADC_0 low reference voltage ADC_1 high reference voltage ADC_1 low reference voltage ADC voltage supply for ADC_0 and ADC_1 ADC ground for ADC_0 and ADC_1 Power supply pins (3.3 V) VDD_HV_IO VSS_HV_IO 3.3 V Input/Output supply voltage 3.3 V Input/Output ground 6 7 16 21 22 27 28 90 91 95 96 97 126 127 130 Power supply pins (1.2 V) VDD_HV3 VSS_HV4 J3 VDD_HV3 VSS_HV4 M1 P1 VSS_HV4 VDD_HV3 H15 J16 H16 VDD_HV3 VSS_HV4 C7 50 51 56 57 58 59 R7 T7 R9 T9 U9 U10 69 70 71 72 R13 VDD_LV1 VSS_LV2 U14 Pin # 144 pkg 257 pkg
VDD_HV_REG_0 VDD_HV_REG_0 VDD_HV_IO VSS_HV_IO VDD_HV_OSC VSS_HV_OSC VSS_HV_IO VDD_HV_IO 3.3 V Input/Output supply voltage 3.3 V Input/Output ground Crystal oscillator amplifier supply voltage Crystal oscillator amplifier ground 3.3 V Input/Output ground 3.3 V Input/Output supply voltage
VDD_HV_REG_1 VDD_HV_REG_1 VSS_HV_FLA VDD_HV_FLA VDD_HV_IO VSS_HV_IO VSS_HV_FLA VDD_HV_FLA VDD_HV_IO VSS_HV_IO
VDD_HV_REG_2 VDD_HV_REG_2
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 51
Package pinouts and signal descriptions
Table 5. Supply pins (continued)
Supply Symbol VSS_LV_COR Description VSS_LV_COR Decoupling pins for core logic. Decoupling capacitor must be connected between these pins and the nearest VDD_LV_COR pin. VDD_LV_COR Decoupling pins for core logic. Decoupling capacitor must be connected between these pins and the nearest VSS_LV_COR pin. VSS_LV_PLL0_PLL1 / 1.2 V Decoupling pins for on-chip FMPLL modules. Decoupling capacitor must be connected between this pin and VDD_LV_PLL. VDD_LV_PLL0_PLL1 Decoupling pins for on-chip FMPLL modules. Decoupling capacitor must be connected between this pin and VSS_LV_PLL. VDD_LV_COR Decoupling pins for core logic. Decoupling capacitor must be connected between these pins and the nearest VSS_LV_COR pin. VSS_LV_COR Decoupling pins for core logic. Decoupling capacitor must be connected between these pins and the nearest VDD_LV_COR pin. VDD_LV_COR Decoupling pins for core logic and Regulator feedback. Decoupling capacitor must be connected between this pins and VSS_LV_REGCOR. VSS_LV_REGCOR0 Decoupling pins for core logic and Regulator feedback. Decoupling capacitor must be connected between this pins and VDD_LV_REGCOR. VDD_LV_COR Decoupling pins for core logic. Decoupling capacitor must be connected between these pins and the nearest VSS_LV_COR pin. VSS_LV_COR / 1.2 V Decoupling pins for core logic. Decoupling capacitor must be connected between these pins and the nearest VDD_LV_COR pin. VDD_LV_COR Decoupling pins for core logic. Decoupling capacitor must be connected between these pins and the nearest VDD_LV_COR pin. VSS_LV_COR Decoupling pins for core logic. Decoupling capacitor must be connected between these pins and the nearest VDD_LV_COR pin. VDD_LV_COR / Decoupling pins for core logic. Decoupling capacitor must be connected between these pins and the nearest VDD_LV_COR pin. VSS_LV_COR / Decoupling pins for core logic. Decoupling capacitor must be connected between these pins and the nearest VDD_LV_COR pin. Pin # 144 pkg 17 257 pkg VSS_HV2
VDD_LV_COR
18
VDD_LV1
VSS 1V2
35
N4
VDD 1V2
36
P4
VDD_LV_COR
39
VDD_LV1
VSS_LV_COR
40
VSS_LV2
VDD_LV_COR
70
VDD_LV1
VSS_LV_COR
71
VSS_LV2
VDD_LV_COR
93
VDD_LV1
VSS_LV_COR
94
VSS_LV2
VDD 1V2
131
VDD_LV1
VSS 1V2
132
VSS_LV2
VDD 1V2
135
VDD_LV1
VSS 1V2
137
VSS_LV2
1
VDD_LV balls are tied together on the 257 MAPBGA substrate.
MPC5643L Microcontroller Data Sheet, Rev. 6 52 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Package pinouts and signal descriptions
2 3
VSS_LV balls are tied together on the 257 MAPBGA substrate. VDD_HV balls are tied together on the 257 MAPBGA substrate. 4 VSS_HV balls are tied together on the 257 MAPBGA substrate.
2.3
System pins
Table 6. System pins
Pin # Symbol Description Direction 144 pkg 257 pkg
Dedicated pins MDO01 NMI
2
Nexus Message Data Output -- line 0 Non Maskable Interrupt Input for oscillator amplifier circuit and internal clock generator Oscillator amplifier output JTAG state machine control JTAG clock
Output only Input only Input only Output only Input only Input only Input only
9 1 29 30 87 88 123
E1 E4 N1 R1 M16 L15 C10
XTAL EXTAL TMS2 TCK2 JCOMP
3
JTAG compliance select Reset pin
RESET
Bidirectional reset with Schmitt-Trigger characteristics and noise filter. Bidirectional This pin has medium drive strength. Test pin
31
P2
VPP TEST
1 2
Pin for testing purpose only. To be tied to ground in normal operating mode.
107
D15
This pad is configured for Fast (F) pad speed. This pad contains a weak pull-up. 3 This pad contains a weak pull-down.
2.4
Pin muxing
Table 7 defines the pin list and muxing for this device. Each entry of Table 7 shows all the possible configurations for each pin, via the alternate functions. The default function assigned to each pin after reset is indicated by ALT0.
NOTE
Pins labeled "NC" are to be left unconnected. Any connection to an external circuit or voltage may cause unpredictable device behavior or damage. Pins labeled "Reserved" are to be tied to ground. Not doing so may cause unpredictable device behavior.
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 53
54
Package pinouts and signal descriptions
Table 7. Pin muxing
Port name Alternate output function Output mux sel Input functions Port A A[0] PCR[0] SIUL eTimer_0 DSPI_2 Preliminary--Subject to Change Without Notice Freescale Semiconductor SIUL A[1] PCR[1] SIUL eTimer_0 DSPI_2 SIUL A[2] PCR[2] SIUL eTimer_0 FlexPWM_0 DSPI_2 MC_RGM SIUL A[3] PCR[3] SIUL eTimer_0 DSPI_2 FlexPWM_0 MC_RGM SIUL MPC5643L Microcontroller Data Sheet, Rev. 6 GPIO[0] ETC[0] SCK -- GPIO[1] ETC[1] SOUT -- GPIO[2] ETC[2] A[3] -- -- -- GPIO[3] ETC[3] CS0 B[3] -- -- ALT0 ALT1 ALT2 -- ALT0 ALT1 ALT2 -- ALT0 ALT1 ALT3 -- -- -- ALT0 ALT1 ALT2 ALT3 -- -- GPIO[0] ETC[0] SCK EIRQ[0] GPIO[1] ETC[1] -- EIRQ[1] GPIO[2] ETC[2] A[3] SIN ABS[0] EIRQ[2] GPIO[3] ETC[3] CS0 B[3] ABS[2] EIRQ[3] -- PSMI[35]; PADSEL=0 PSMI[1]; PADSEL=0 -- -- PSMI[36]; PADSEL=0 -- -- -- PSMI[37]; PADSEL=0 PSMI[23]; PADSEL=0 PSMI[2]; PADSEL=0 -- -- -- PSMI[38]; PADSEL=0 PSMI[3]; PADSEL=0 PSMI[27]; PADSEL=0 -- -- Pull down M S 92 K17 Pull down M S 84 N16 Pull down M S 74 R14 Pull down M S 73 T14 Pad speed1 Weak pull config during SRC SRC reset =1 =0 Pin # 144 pkg 257 pkg
PCR
Peripheral
Input mux select
Table 7. Pin muxing (continued)
Port name A[4] Alternate output function GPIO[4] ETC[0] CS1 ETC[4] -- -- GPIO[5] CS0 ETC[5] CS7 -- GPIO[6] SCK -- GPIO[7] SOUT -- GPIO[8] -- -- GPIO[9] CS1 B[3] -- Output mux sel ALT0 ALT1 ALT2 ALT3 -- -- ALT0 ALT1 ALT2 ALT3 -- ALT0 ALT1 -- ALT0 ALT1 -- ALT0 -- -- ALT0 ALT1 ALT3 -- Input functions GPIO[4] ETC[0] -- ETC[4] FAB EIRQ[4] GPIO[5] CS0 ETC[5] -- EIRQ[5] GPIO[6] SCK EIRQ[6] GPIO[7] -- EIRQ[7] GPIO[8] SIN EIRQ[8] GPIO[9] -- B[3] FAULT[0] Pad speed1 Weak pull config during SRC SRC reset =1 =0 Pull down M S Pin # 144 pkg 108 257 pkg C16
Freescale Semiconductor Preliminary--Subject to Change Without Notice 55 MPC5643L Microcontroller Data Sheet, Rev. 6
PCR
Peripheral
Input mux select
PCR[4]
SIUL eTimer_1 DSPI_2 eTimer_0 MC_RGM SIUL
-- PSMI[9]; PADSEL=0 -- PSMI[7]; PADSEL=0 -- -- -- -- PSMI[14]; PADSEL=0 -- -- -- -- -- -- -- -- -- -- -- -- -- PSMI[27]; PADSEL=1 PSMI[16]; PADSEL=0
A[5]
PCR[5]
SIUL DSPI_1 eTimer_1 DSPI_0 SIUL
Pull down
M
S
14
H4
A[6]
PCR[6]
SIUL DSPI_1 SIUL
Pull down
M
S
2
G4
A[7]
PCR[7]
SIUL DSPI_1 SIUL
Pull down
M
S
10
F3 Package pinouts and signal descriptions
A[8]
PCR[8]
SIUL DSPI_1 SIUL
Pull down
M
S
12
F4
A[9]
PCR[9]
SIUL DSPI_2 FlexPWM_0 FlexPWM_0
Pull down
M
S
134
B6
Table 7. Pin muxing (continued)
Port name A[10] Alternate output function GPIO[10] CS0 B[0] X[2] -- GPIO[11] SCK A[0] A[2] -- GPIO[12] SOUT A[2] B[2] -- GPIO[13] B[2] -- -- -- GPIO[14] TXD ETC[4] -- Output mux sel ALT0 ALT1 ALT2 ALT3 -- ALT0 ALT1 ALT2 ALT3 -- ALT0 ALT1 ALT2 ALT3 -- ALT0 ALT2 -- -- -- ALT0 ALT1 ALT2 -- Input functions GPIO[10] CS0 B[0] X[2] EIRQ[9] GPIO[11] SCK A[0] A[2] EIRQ[10] GPIO[12] -- A[2] B[2] EIRQ[11] GPIO[13] B[2] SIN FAULT[0] EIRQ[12] GPIO[14] -- ETC[4] EIRQ[13] Pad speed1 Weak pull config during SRC SRC reset =1 =0 Pull down M S Pin # 144 pkg 118 257 pkg A13
56 PCR Peripheral PCR[10] SIUL DSPI_2 FlexPWM_0 FlexPWM_0 SIUL Preliminary--Subject to Change Without Notice Freescale Semiconductor MPC5643L Microcontroller Data Sheet, Rev. 6 A[11] PCR[11] SIUL DSPI_2 FlexPWM_0 FlexPWM_0 SIUL A[12] PCR[12] SIUL DSPI_2 FlexPWM_0 FlexPWM_0 SIUL A[13] PCR[13] SIUL FlexPWM_0 DSPI_2 FlexPWM_0 SIUL A[14] PCR[14] SIUL FlexCAN_1 eTimer_1 SIUL
Package pinouts and signal descriptions
Input mux select
-- PSMI[3]; PADSEL=1 PSMI[24]; PADSEL=0 PSMI[29]; PADSEL=0 -- -- PSMI[1]; PADSEL=1 PSMI[20]; PADSEL=0 PSMI[22]; PADSEL=0 -- -- -- PSMI[22]; PADSEL=1 PSMI[26]; PADSEL=0 -- -- PSMI[26]; PADSEL=1 PSMI[2]; PADSEL=1 PSMI[16]; PADSEL=1 -- -- -- PSMI[13]; PADSEL=0 --
Pull down
M
S
120
D11
Pull down
M
S
122
A10
Pull down
M
S
136
C6
Pull down
M
S
143
B4
Table 7. Pin muxing (continued)
Port name A[15] Alternate output function GPIO[15] ETC[5] -- -- -- Output mux sel ALT0 ALT2 -- -- -- Input functions GPIO[15] ETC[5] RXD RXD EIRQ[14] Port B B[0] PCR[16] SIUL FlexCAN_0 eTimer_1 SSCM SIUL B[1] PCR[17] SIUL eTimer_1 SSCM FlexCAN_0 FlexCAN_1 SIUL B[2] PCR[18] SIUL LINFlex_0 SSCM SIUL B[3] PCR[19] SIUL SSCM LINFlex_0 GPIO[16] TXD ETC[2] DEBUG[0] -- GPIO[17] ETC[3] DEBUG[1] -- -- -- GPIO[18] TXD DEBUG[2] -- GPIO[19] DEBUG[3] -- ALT0 ALT1 ALT2 ALT3 -- ALT0 ALT2 ALT3 -- -- -- ALT0 ALT1 ALT3 -- ALT0 ALT3 -- GPIO[16] -- ETC[2] -- EIRQ[15] GPIO[17] ETC[3] -- RXD RXD EIRQ[16] GPIO[18] -- -- EIRQ[17] GPIO[19] -- RXD -- -- PSMI[11]; PADSEL=0 -- -- -- PSMI[12]; PADSEL=0 -- PSMI[33]; PADSEL=1 PSMI[34]; PADSEL=1 -- -- -- -- -- -- -- PSMI[31]; PADSEL=0 Pull down M S 116 B13 Pull down M S 114 A14 Package pinouts and signal descriptions Pull down M S 110 C14 Pull down M S 109 B15 Pad speed1 Weak pull config during SRC SRC reset =1 =0 Pull down M S Pin # 144 pkg 144 257 pkg D3
Freescale Semiconductor Preliminary--Subject to Change Without Notice 57 MPC5643L Microcontroller Data Sheet, Rev. 6
PCR
Peripheral
Input mux select
PCR[15]
SIUL eTimer_1 FlexCAN_1 FlexCAN_0 SIUL
-- PSMI[14]; PADSEL=1 PSMI[34]; PADSEL=0 PSMI[33]; PADSEL=0 --
Table 7. Pin muxing (continued)
Port name B[4]2 Alternate output function GPIO[20] TDO GPIO[21] -- GPIO[22] clk_out CS2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ALT0 -- -- ALT0 -- -- ALT0 -- ALT0 -- ALT0 -- ALT0 -- Output mux sel ALT0 ALT1 ALT0 -- ALT0 ALT1 ALT2 Input functions GPIO[20] -- GPIO[21] TDI GPIO[22] -- -- EIRQ[18] GPI[23] RXD AN[0]
3
58 PCR Peripheral PCR[20] SIUL JTAGC B[5] PCR[21] SIUL JTAGC B[6] Preliminary--Subject to Change Without Notice Freescale Semiconductor MPC5643L Microcontroller Data Sheet, Rev. 6 PCR[22] SIUL MC_CGM DSPI_2 SIUL B[7] PCR[23] SIUL LINFlex_0 ADC_0 B[8] PCR[24] SIUL eTimer_0 ADC_0 B[9] PCR[25] SIUL ADC_0 ADC_1 B[10] PCR[26] SIUL ADC_0 ADC_1 B[11] PCR[27] SIUL ADC_0 ADC_1 B[12] PCR[28] SIUL ADC_0 ADC_1
Package pinouts and signal descriptions
Input mux select
Pad speed1 Weak pull config during SRC SRC reset =1 =0 Pull down F S
Pin # 144 pkg 89 257 pkg L17
-- -- -- -- -- -- -- -- -- PSMI[31]; PADSEL=1 -- -- PSMI[8]; PADSEL=2 -- -- -- -- -- -- -- -- --
Pull up
M
S
86
M15
Pull down
F
S
138
B3
--
--
--
43
R5
GPI[24] ETC[5] AN[1]
3
--
--
--
47
P7
GPI[25] AN[11]3 GPI[26] AN[12]3 GPI[27] AN[13]3 GPI[28] AN[14]
3
--
--
--
52
U7
--
--
--
53
R8
--
--
--
54
T8
--
--
--
55
U8
Table 7. Pin muxing (continued)
Port name B[13] Alternate output function -- -- -- -- -- -- -- -- -- -- Output mux sel ALT0 -- -- ALT0 -- -- -- ALT0 -- -- Input functions GPI[29] RXD AN[0]
3
Freescale Semiconductor Preliminary--Subject to Change Without Notice 59 MPC5643L Microcontroller Data Sheet, Rev. 6
PCR
Peripheral
Input mux select
Pad speed1 Weak pull config during SRC SRC reset =1 =0 -- -- --
Pin # 144 pkg 60 257 pkg R10
PCR[29]
SIUL LINFlex_1 ADC_1
-- PSMI[32]; PADSEL=0 -- -- PSMI[7]; PADSEL=2 -- -- -- -- --
B[14]
PCR[30]
SIUL eTimer_0 SIUL ADC_1
GPI[30] ETC[4] EIRQ[19] AN[1]
3
--
--
--
64
P11
B[15]
PCR[31]
SIUL SIUL ADC_1
GPI[31] EIRQ[20] AN[2]
3
--
--
--
62
R11
Port C C[0] PCR[32] SIUL ADC_1 C[1] PCR[33] SIUL ADC_0 C[2] PCR[34] SIUL ADC_0 C[4] PCR[36] SIUL DSPI_0 FlexPWM_0 SSCM SIUL -- -- -- -- -- -- GPIO[36] CS0 X[1] DEBUG[4] -- ALT0 -- ALT0 -- ALT0 -- ALT0 ALT1 ALT2 ALT3 -- GPI[32] AN[3]3 GPI[33] AN[2]
3
-- -- -- -- -- -- -- -- PSMI[28]; PADSEL=0 -- --
--
--
--
66
R12
--
--
--
41
T4
GPI[34] AN[3]3 GPIO[36] CS0 X[1] -- EIRQ[22]
--
--
--
45
U5
Package pinouts and signal descriptions
Pull down
M
S
11
H3
Table 7. Pin muxing (continued)
Port name C[5] Alternate output function GPIO[37] SCK DEBUG[5] -- -- GPIO[38] SOUT B[1] DEBUG[6] -- GPIO[39] A[1] DEBUG[7] -- GPIO[42] CS2 A[3] -- GPIO[43] ETC[4] CS2 GPIO[44] ETC[5] CS3 Output mux sel ALT0 ALT1 ALT3 -- -- ALT0 ALT1 ALT2 ALT3 -- ALT0 ALT2 ALT3 -- ALT0 ALT1 ALT3 -- ALT0 ALT1 ALT2 ALT0 ALT1 ALT2 Input functions GPIO[37] SCK -- FAULT[3] EIRQ[23] GPIO[38] -- B[1] -- EIRQ[24] GPIO[39] A[1] -- SIN GPIO[42] -- A[3] FAULT[1] GPIO[43] ETC[4] -- GPIO[44] ETC[5] -- Pad speed1 Weak pull config during SRC SRC reset =1 =0 Pull down M S Pin # 144 pkg 13 257 pkg G3
60 PCR Peripheral PCR[37] SIUL DSPI_0 SSCM FlexPWM_0 SIUL Preliminary--Subject to Change Without Notice Freescale Semiconductor MPC5643L Microcontroller Data Sheet, Rev. 6 C[6] PCR[38] SIUL DSPI_0 FlexPWM_0 SSCM SIUL C[7] PCR[39] SIUL FlexPWM_0 SSCM DSPI_0 C[10] PCR[42] SIUL DSPI_2 FlexPWM_0 FlexPWM_0 C[11] PCR[43] SIUL eTimer_0 DSPI_2 C[12] PCR[44] SIUL eTimer_0 DSPI_2
Package pinouts and signal descriptions
Input mux select
-- -- -- PSMI[19]; PADSEL=0 -- -- -- PSMI[25]; PADSEL=0 -- -- -- PSMI[21]; PADSEL=0 -- -- -- -- PSMI[23]; PADSEL=1 PSMI[17]; PADSEL=0 -- PSMI[7]; PADSEL=1 -- -- PSMI[8]; PADSEL=0 --
Pull down
M
S
142
D4
Pull down
M
S
15
K4
Pull down
M
S
111
A15
Pull down
M
S
80
M14
Pull down
M
S
82
N15
Table 7. Pin muxing (continued)
Port name C[13] Alternate output function GPIO[45] ETC[1] -- -- GPIO[46] ETC[2] EXT_TGR GPIO[47] CA_TR_EN ETC[0] A[1] -- -- Output mux sel ALT0 ALT1 -- -- ALT0 ALT1 ALT2 ALT0 ALT1 ALT2 ALT3 -- -- Input functions GPIO[45] ETC[1] EXT_IN EXT_SYNC GPIO[46] ETC[2] -- GPIO[47] -- ETC[0] A[1] EXT_IN EXT_SYNC Port D D[0] PCR[48] SIUL FlexRay eTimer_1 FlexPWM_0 D[1] PCR[49] SIUL eTimer_1 CTU_0 FlexRay GPIO[48] CA_TX ETC[1] B[1] GPIO[49] ETC[2] EXT_TGR -- ALT0 ALT1 ALT2 ALT3 ALT0 ALT2 ALT3 -- GPIO[48] -- ETC[1] B[1] GPIO[49] ETC[2] -- CA_RX -- -- PSMI[10]; PADSEL=1 PSMI[25]; PADSEL=1 -- PSMI[11]; PADSEL=2 -- -- Pull down M S 3 E3 Pull down SYM S 125 B8 Package pinouts and signal descriptions Pad speed1 Weak pull config during SRC SRC reset =1 =0 Pull down M S Pin # 144 pkg 101 257 pkg F15
Freescale Semiconductor Preliminary--Subject to Change Without Notice 61 MPC5643L Microcontroller Data Sheet, Rev. 6
PCR
Peripheral
Input mux select
PCR[45]
SIUL eTimer_1 CTU_0 FlexPWM_0
-- PSMI[10]; PADSEL=0 PSMI[0]; PADSEL=0 PSMI[15]; PADSEL=0 -- PSMI[11]; PADSEL=1 -- -- -- PSMI[9]; PADSEL=1 PSMI[21]; PADSEL=1 PSMI[0]; PADSEL=1 PSMI[15]; PADSEL=1
C[14]
PCR[46]
SIUL eTimer_1 CTU_0
Pull down
M
S
103
E15
C[15]
PCR[47]
SIUL FlexRay eTimer_1 FlexPWM_0 CTU_0 FlexPWM_0
Pull down
SYM
S
124
A8
Table 7. Pin muxing (continued)
Port name D[2] Alternate output function GPIO[50] ETC[3] X[3] -- GPIO[51] CB_TX ETC[4] A[3] GPIO[52] CB_TR_EN ETC[5] B[3] GPIO[53] CS3 -- GPIO[54] CS2 X[3] -- GPIO[55] CS3 CS4 analog output Output mux sel ALT0 ALT2 ALT3 -- ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 -- ALT0 ALT1 ALT3 -- ALT0 ALT1 ALT3 -- Input functions GPIO[50] ETC[3] X[3] CB_RX GPIO[51] -- ETC[4] A[3] GPIO[52] -- ETC[5] B[3] GPIO[53] -- FAULT[2] GPIO[54] -- X[3] FAULT[1] GPIO[55] -- -- -- Pad speed1 Weak pull config during SRC SRC reset =1 =0 Pull down M S Pin # 144 pkg 140 257 pkg C5
62 PCR Peripheral PCR[50] SIUL eTimer_1 FlexPWM_0 FlexRay D[3] Preliminary--Subject to Change Without Notice Freescale Semiconductor MPC5643L Microcontroller Data Sheet, Rev. 6 PCR[51] SIUL FlexRay eTimer_1 FlexPWM_0 D[4] PCR[52] SIUL FlexRay eTimer_1 FlexPWM_0 D[5] PCR[53] SIUL DSPI_0 FlexPWM_0 D[6] PCR[54] SIUL DSPI_0 FlexPWM_0 FlexPWM_0 D[7] PCR[55] SIUL DSPI_1 DSPI_0 SWG
Package pinouts and signal descriptions
Input mux select
-- PSMI[12]; PADSEL=1 PSMI[30]; PADSEL=0 -- -- -- PSMI[13]; PADSEL=1 PSMI[23]; PADSEL=2 -- -- PSMI[14]; PADSEL=2 PSMI[27]; PADSEL=2 -- -- PSMI[18]; PADSEL=0 -- -- PSMI[30]; PADSEL=1 PSMI[17]; PADSEL=1 -- -- -- --
Pull down
SYM
S
128
A7
Pull down
SYM
S
129
B7
Pull down
M
S
33
N3
Pull down
M
S
34
P3
Pull down
M
S
37
R4
Table 7. Pin muxing (continued)
Port name D[8] Alternate output function GPIO[56] CS2 ETC[4] CS5 -- GPIO[57] X[0] TXD GPIO[58] A[0] -- GPIO[59] B[0] -- GPIO[60] X[1] -- GPIO[62] B[1] -- Output mux sel ALT0 ALT1 ALT2 ALT3 -- ALT0 ALT1 ALT2 ALT0 ALT1 -- ALT0 ALT1 -- ALT0 ALT1 -- ALT0 ALT1 -- Input functions GPIO[56] -- ETC[4] -- FAULT[3] GPIO[57] X[0] -- GPIO[58] A[0] ETC[0] GPIO[59] B[0] ETC[1] GPIO[60] X[1] RXD GPIO[62] B[1] ETC[3] Port E E[0] PCR[64] SIUL ADC_1 E[2] PCR[66] SIUL ADC_0 -- -- -- -- ALT0 -- ALT0 -- GPI[64] AN[5]3 GPI[66] AN[5]3 -- -- -- -- -- -- -- 49 U6 -- -- -- 68 T13 PSMI[28]; PADSEL=1 PSMI[32]; PADSEL=1 -- PSMI[25]; PADSEL=2 PSMI[38]; PADSEL=1 Pull down M S 105 D16 Pad speed1 Weak pull config during SRC SRC reset =1 =0 Pull down M S Pin # 144 pkg 32 257 pkg M3
Freescale Semiconductor Preliminary--Subject to Change Without Notice 63 MPC5643L Microcontroller Data Sheet, Rev. 6
PCR
Peripheral
Input mux select
PCR[56]
SIUL DSPI_1 eTimer_1 DSPI_0 FlexPWM_0
-- -- PSMI[13]; PADSEL=2 -- PSMI[19]; PADSEL=1 -- -- -- -- PSMI[20]; PADSEL=1 PSMI[35]; PADSEL=1 -- PSMI[24]; PADSEL=1 PSMI[36]; PADSEL=1
D[9]
PCR[57]
SIUL FlexPWM_0 LINFlexD_1
Pull down
M
S
26
L3
D[10]
PCR[58]
SIUL FlexPWM_0 eTimer_0
Pull down
M
S
76
T15
D[11]
PCR[59]
SIUL FlexPWM_0 eTimer_0
Pull down
M
S
78
R16
D[12]
PCR[60]
SIUL FlexPWM_0 LINFlexD_1
Pull down
M
S
99
G14 Package pinouts and signal descriptions
D[14]
PCR[62]
SIUL FlexPWM_0 eTimer_0
Table 7. Pin muxing (continued)
Port name E[4] Alternate output function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- GPIO[77] ETC[5] CS3 -- GPIO[78] ETC[5] -- Output mux sel ALT0 -- ALT0 -- ALT0 -- ALT0 -- ALT0 -- ALT0 -- ALT0 -- ALT0 -- ALT0 ALT1 ALT2 -- ALT0 ALT1 -- Input functions GPI[68] AN[7]
3
64 PCR Peripheral PCR[68] SIUL ADC_0 E[5] PCR[69] SIUL ADC_0 E[6] Preliminary--Subject to Change Without Notice Freescale Semiconductor MPC5643L Microcontroller Data Sheet, Rev. 6 PCR[70] SIUL ADC_0 E[7] PCR[71] SIUL ADC_0 E[9] PCR[73] SIUL ADC_1 E[10] PCR[74] SIUL ADC_1 E[11] PCR[75] SIUL ADC_1 E[12] PCR[76] SIUL ADC_1 E[13] PCR[77] SIUL eTimer_0 DSPI_2 SIUL E[14] PCR[78] SIUL eTimer_1 SIUL
Package pinouts and signal descriptions
Input mux select
Pad speed1 Weak pull config during SRC SRC reset =1 =0 -- -- --
Pin # 144 pkg 42 257 pkg U4
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PSMI[8]; PADSEL=1 -- -- -- PSMI[14]; PADSEL=3 --
GPI[69] AN[8]3 GPI[70] AN[4]
3
--
--
--
44
T5
--
--
--
46
R6
GPI[71] AN[6]3 GPI[73] AN[7]3 GPI[74] AN[8]3 GPI[75] AN[4]3 GPI[76] AN[6]3 GPIO[77] ETC[5] -- EIRQ[25] GPIO[78] ETC[5] EIRQ[26]
--
--
--
48
T6
--
--
--
61
T10
--
--
--
63
T11
--
--
--
65
U11
--
--
--
67
T12
Pull down
M
S
117
D12
Pull down
M
S
119
B12
Table 7. Pin muxing (continued)
Port name E[15] Alternate output function GPIO[79] CS1 -- Output mux sel ALT0 ALT1 -- Input functions GPIO[79] -- EIRQ[27] Port F F[0] PCR[80] SIUL FlexPWM_0 eTimer_0 SIUL F[3] PCR[83] SIUL DSPI_0 F[4] PCR[84] SIUL NPC F[5] PCR[85] SIUL NPC F[6] PCR[86] SIUL NPC F[7] PCR[87] SIUL NPC F[8] PCR[88] SIUL NPC F[9] PCR[89] SIUL NPC F[10] PCR[90] SIUL NPC GPIO[80] A[1] -- -- GPIO[83] CS6 GPIO[84] MDO[3] GPIO[85] MDO[2] GPIO[86] MDO[1] GPIO[87] MCKO GPIO[88] MSEO[1] GPIO[89] MSEO[0] GPIO[90] EVTO ALT0 ALT1 -- -- ALT0 ALT1 ALT0 ALT2 ALT0 ALT2 ALT0 ALT2 ALT0 ALT2 ALT0 ALT2 ALT0 ALT2 ALT0 ALT2 GPIO[80] A[1] ETC[2] EIRQ[28] GPIO[83] -- GPIO[84] -- GPIO[85] -- GPIO[86] -- GPIO[87] -- GPIO[88] -- GPIO[89] -- GPIO[90] -- -- PSMI[21]; PADSEL=2 PSMI[37]; PADSEL=1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Pull down F S 24 L1 Pull down F S 23 K1 Pull down F S 20 K2 Pull down F S 19 J1 Pull down F S 8 E2 Package pinouts and signal descriptions Pull down F S 5 D1 Pull down F S 4 D2 Pull down M S 139 B5 Pull down M S 133 D7 Pad speed1 Weak pull config during SRC SRC reset =1 =0 Pull down M S Pin # 144 pkg 121 257 pkg B11
Freescale Semiconductor Preliminary--Subject to Change Without Notice 65 MPC5643L Microcontroller Data Sheet, Rev. 6
PCR
Peripheral
Input mux select
PCR[79]
SIUL DSPI_0 SIUL
-- -- --
Table 7. Pin muxing (continued)
Port name F[11] Alternate output function GPIO[91] EVTI GPIO[92] ETC[3] -- GPIO[93] ETC[4] -- GPIO[94] TXD GPIO[95] -- Output mux sel ALT0 ALT2 ALT0 ALT1 -- ALT0 ALT1 -- ALT0 ALT1 ALT0 -- Input functions GPIO[91] -- GPIO[92] ETC[3] EIRQ[30] GPIO[93] ETC[4] EIRQ[31] GPIO[94] -- GPIO[95] RXD FCCU FCCU_ F[0] FCCU_ F[1] -- -- FCCU FCCU F[0] F[1] ALT0 ALT0 F[0] F[1] Port G G[2] PCR[98] SIUL FlexPWM_0 DSPI_1 G[3] PCR[99] SIUL FlexPWM_0 eTimer_0 GPIO[98] X[2] CS1 GPIO[99] A[2] -- ALT0 ALT1 ALT2 ALT0 ALT1 -- GPIO[98] X[2] -- GPIO[99] A[2] ETC[4] -- PSMI[29]; PADSEL=1 -- -- PSMI[22]; PADSEL=2 PSMI[7]; PADSEL=3 Pull down M S 104 D17 Pull down M S 102 E16 -- -- -- -- S S S S 38 141 R2 C4 Pad speed1 Weak pull config during SRC SRC reset =1 =0 Pull down M S Pin # 144 pkg 25 257 pkg L2
66 PCR Peripheral PCR[91] SIUL NPC F[12] PCR[92] SIUL eTimer_1 SIUL Preliminary--Subject to Change Without Notice Freescale Semiconductor MPC5643L Microcontroller Data Sheet, Rev. 6 F[13] PCR[93] SIUL eTimer_1 SIUL F[14] PCR[94] SIUL LINFlexD_1 F[15] PCR[95] SIUL LINFlexD_1
Package pinouts and signal descriptions
Input mux select
-- -- -- PSMI[12]; PADSEL=2 -- -- PSMI[13]; PADSEL=3 -- -- -- -- PSMI[32]; PADSEL=2
Pull down
M
S
106
C17
Pull down
M
S
112
B14
Pull down
M
S
115
C13
Pull down
M
S
113
D13
Table 7. Pin muxing (continued)
Port name G[4] Alternate output function GPIO[100] B[2] -- GPIO[101] X[3] CS3 GPIO[102] A[3] GPIO[103] B[3] GPIO[104] DBG0 CS1 -- -- GPIO[105] DBG1 CS1 -- -- GPIO[106] DBG2 CS3 -- Output mux sel ALT0 ALT1 -- ALT0 ALT1 ALT2 ALT0 ALT1 ALT0 ALT1 ALT0 ALT1 ALT2 -- -- ALT0 ALT1 ALT2 -- -- ALT0 ALT1 ALT2 -- Input functions GPIO[100] B[2] ETC[5] GPIO[101] X[3] -- GPIO[102] A[3] GPIO[103] B[3] GPIO[104] -- -- FAULT[0] EIRQ[21] GPIO[105] -- -- FAULT[1] EIRQ[29] GPIO[106] -- -- FAULT[2] PSMI[27]; PADSEL=3 -- -- -- PSMI[16]; PADSEL=2 -- -- -- -- PSMI[17]; PADSEL=2 -- -- -- -- PSMI[18]; PADSEL=1 Pull down M S 77 P15 Pull down M S 79 R17 Package pinouts and signal descriptions Pull down M S 81 P16 Pad speed1 Weak pull config during SRC SRC reset =1 =0 Pull down M S Pin # 144 pkg 100 257 pkg F17
Freescale Semiconductor Preliminary--Subject to Change Without Notice 67 MPC5643L Microcontroller Data Sheet, Rev. 6
PCR
Peripheral
Input mux select
PCR[100]
SIUL FlexPWM_0 eTimer_0
-- PSMI[26]; PADSEL=2 PSMI[8]; PADSEL=3 -- PSMI[30]; PADSEL=2 -- -- PSMI[23]; PADSEL=3
G[5]
PCR[101]
SIUL FlexPWM_0 DSPI_2
Pull down
M
S
85
N17
G[6]
PCR[102]
SIUL FlexPWM_0
Pull down
M
S
98
G17
G[7]
PCR[103]
SIUL FlexPWM_0
Pull down
M
S
83
P17
G[8]
PCR[104]
SIUL FlexRay DSPI_0 FlexPWM_0 SIUL
G[9]
PCR[105]
SIUL FlexRay DSPI_1 FlexPWM_0 SIUL
G[10]
PCR[106]
SIUL FlexRay DSPI_2 FlexPWM_0
Table 7. Pin muxing (continued)
Port name G[11] Alternate output function GPIO[107] DBG3 -- GPIO[108] MDO[11] GPIO[109] MDO[10] GPIO[110] MDO[9] GPIO[111] MDO[8] Output mux sel ALT0 ALT1 -- ALT0 ALT2 ALT0 ALT2 ALT0 ALT2 ALT0 ALT2 Input functions GPIO[107] -- FAULT[3] GPIO[108] -- GPIO[109] -- GPIO[110] -- GPIO[111] -- Port H H[0] PCR[112] SIUL NPC H[1] PCR[113] SIUL NPC H[2] PCR[114] SIUL NPC H[3] PCR[115] SIUL NPC H[4] PCR[116] SIUL FlexPWM_1 eTimer_2 GPIO[112] MDO[7] GPIO[113] MDO[6] GPIO[114] MDO[5] GPIO[115] MDO[4] GPIO[116] X[0] ETC[0] ALT0 ALT2 ALT0 ALT2 ALT0 ALT2 ALT0 ALT2 ALT0 ALT1 ALT2 GPIO[112] -- GPIO[113] -- GPIO[114] -- GPIO[115] -- GPIO[116] X[0] ETC[0] -- -- -- -- -- -- -- -- -- -- PSMI[39]; PADSEL=0 Pull down M S -- L16 Pull down F S -- G1 Pull down F S -- A4 Pull down F S -- F1 Pull down F S -- A5 Pad speed1 Weak pull config during SRC SRC reset =1 =0 Pull down M S Pin # 144 pkg 75 257 pkg U15
68 PCR Peripheral PCR[107] SIUL FlexRay FlexPWM_0 G[12] Preliminary--Subject to Change Without Notice Freescale Semiconductor PCR[108] SIUL NPC MPC5643L Microcontroller Data Sheet, Rev. 6 G[13] PCR[109] SIUL NPC G[14] PCR[110] SIUL NPC G[15] PCR[111] SIUL NPC
Package pinouts and signal descriptions
Input mux select
-- -- PSMI[19]; PADSEL=2 -- -- -- -- -- -- -- --
Pull down
F
S
--
F2
Pull down
F
S
--
H1
Pull down
F
S
--
A6
Pull down
F
S
--
J2
Table 7. Pin muxing (continued)
Port name H[5] Alternate output function GPIO[117] A[0] CS4 GPIO[118] B[0] CS5 GPIO[119] X[1] ETC[1] GPIO[120] A[1] CS6 GPIO[121] B[1] CS7 GPIO[122] X[2] ETC[2] GPIO[123] A[2] GPIO[124] B[2] GPIO[125] X[3] ETC[3] Output mux sel ALT0 ALT1 ALT3 ALT0 ALT1 ALT3 ALT0 ALT1 ALT2 ALT0 ALT1 ALT3 ALT0 ALT1 ALT3 ALT0 ALT1 ALT2 ALT0 ALT1 ALT0 ALT1 ALT0 ALT1 ALT2 Input functions GPIO[117] A[0] -- GPIO[118] B[0] -- GPIO[119] X[1] ETC[1] GPIO[120] A[1] -- GPIO[121] B[1] -- GPIO[122] X[2] ETC[2] GPIO[123] A[2] GPIO[124] B[2] GPIO[125] X[3] ETC[3] Pad speed1 Weak pull config during SRC SRC reset =1 =0 Pull down M S Pin # 144 pkg -- 257 pkg M17
Freescale Semiconductor Preliminary--Subject to Change Without Notice 69 MPC5643L Microcontroller Data Sheet, Rev. 6
PCR
Peripheral
Input mux select
PCR[117]
SIUL FlexPWM_1 DSPI_0
-- -- -- -- -- -- -- -- PSMI[40]; PADSEL=0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PSMI[42]; PADSEL=0
H[6]
PCR[118]
SIUL FlexPWM_1 DSPI_0
Pull down
M
S
--
H17
H[7]
PCR[119]
SIUL FlexPWM_1 eTimer_2
Pull down
M
S
--
K16
H[8]
PCR[120]
SIUL FlexPWM_1 DSPI_0
Pull down
M
S
--
K15
H[9]
PCR[121]
SIUL FlexPWM_1 DSPI_0
Pull down
M
S
--
G16
H[10]
PCR[122]
SIUL FlexPWM_1 eTimer_2
Pull down
M
S
--
A11
Package pinouts and signal descriptions
H[11]
PCR[123]
SIUL FlexPWM_1
Pull down
M
S
--
C11
H[12]
PCR[124]
SIUL FlexPWM_1
Pull down
M
S
--
B10
H[13]
PCR[125]
SIUL FlexPWM_1 eTimer_2
Pull down
M
S
--
G15
Table 7. Pin muxing (continued)
Port name H[14] Alternate output function GPIO[126] A[3] ETC[4] GPIO[127] B[3] ETC[5] Output mux sel ALT0 ALT1 ALT2 ALT0 ALT1 ALT2 Input functions GPIO[126] A[3] ETC[4] GPIO[127] B[3] ETC[5] Port I I[0] PCR[128] SIUL eTimer_2 DSPI_0 FlexPWM_1 I[1] PCR[129] SIUL eTimer_2 DSPI_0 FlexPWM_1 I[2] PCR[130] SIUL eTimer_2 DSPI_0 FlexPWM_1 GPIO[128] ETC[0] CS4 -- GPIO[129] ETC[1] CS5 -- GPIO[130] ETC[2] CS6 -- ALT0 ALT1 ALT2 -- ALT0 ALT1 ALT2 -- ALT0 ALT1 ALT2 -- GPIO[128] ETC[0] -- FAULT[0] GPIO[129] ETC[1] -- FAULT[1] GPIO[130] ETC[2] -- FAULT[2] -- PSMI[39]; PADSEL=1 -- -- -- PSMI[40]; PADSEL=1 -- -- -- PSMI[41]; PADSEL=1 -- -- Pull down M S -- F16 Pull down M S -- C12 Pull down M S -- C9 Pad speed1 Weak pull config during SRC SRC reset =1 =0 Pull down M S Pin # 144 pkg -- 257 pkg A12
70 PCR Peripheral PCR[126] SIUL FlexPWM_1 eTimer_2 H[15] Preliminary--Subject to Change Without Notice Freescale Semiconductor PCR[127] SIUL FlexPWM_1 MPC5643L Microcontroller Data Sheet, Rev. 6 eTimer_2
Package pinouts and signal descriptions
Input mux select
-- -- -- -- -- --
Pull down
M
S
--
J17
Table 7. Pin muxing (continued)
Port name I[3] Alternate output function GPIO[131] ETC[3] CS7 EXT_TGR -- GPIO[132] RDY Output mux sel ALT0 ALT1 ALT2 ALT3 -- ALT0 ALT2 Input functions GPIO[131] ETC[3] -- -- FAULT[3] GPIO[132] -- Pad speed1 Weak pull config during SRC SRC reset =1 =0 Pull down M S Pin # 144 pkg -- 257 pkg E17
Freescale Semiconductor Preliminary--Subject to Change Without Notice 71 MPC5643L Microcontroller Data Sheet, Rev. 6
1
PCR
Peripheral
Input mux select
PCR[131]
SIUL eTimer_2 DSPI_0 CTU_0 FlexPWM_1
-- PSMI[42]; PADSEL=1 -- -- -- -- --
RDY (cut2 only)
PCR[132] (cut2 only)
SIUL NPC
Pull down
F
S
--
K3 (cut2 only)
Programmable via the SRC (Slew Rate Control) bit in the respective Pad Configuration Register; S = Slow, M = Medium, F = Fast, SYM = Symmetric (for FlexRay) 2 The default function of this pin out of reset is ALT1 (TDO). 3 Analog
Package pinouts and signal descriptions
Electrical characteristics
3
3.1
Electrical characteristics
Introduction
This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for this device. This device is designed to operate at 120 MHz. The electrical specifications are preliminary and are from previous designs, design simulations, or initial evaluation. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published after complete characterization and device qualifications have been completed. The "Symbol" column of the electrical parameter and timings tables contains an additional column containing "SR", "CC", "P", "C", "T", or "D". * * * "SR" identifies system requirements--conditions that must be provided to ensure normal device operation. An example is the input voltage of a voltage regulator. "CC" identifies controller characteristics--indicating the characteristics and timing of the signals that the chip provides. "P", "C", "T", or "D" apply only to controller characteristics--specifications that define normal device operation. They specify how each characteristic is guaranteed. -- P: parameter is guaranteed by production testing of each individual device. -- C: parameter is guaranteed by design characterization. Measurements are taken from a statistically relevant sample size across process variations. -- T: parameter is guaranteed by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values are shown in the typical ("typ") column are within this category. -- D: parameters are derived mainly from simulations.
3.2
Absolute maximum ratings
Table 8. Absolute maximum ratings1
Symbol VDD_HV_REG VSS_HV_REG VDD_HV_IOx VSS_HV_IOx VDD_HV_FLA VSS_HV_FLA VDD_HV_OSC VSS_HV_OSC SR SR SR SR SR SR SR SR Parameter 3.3 V voltage regulator supply voltage 3.3 V voltage regulator reference voltage 3.3 V input/output supply voltage Input/output ground voltage 3.3 V flash supply voltage Flash memory ground 3.3 V crystal oscillator amplifier supply voltage 3.3 V crystal oscillator amplifier reference voltage 3.3 V / 5.0 V ADC_0 high reference voltage 3.3 V / 5.0 V ADC_1 high reference voltage ADC_0 ground and low reference voltage ADC_1 ground and low reference voltage 3.3 V ADC supply voltage Conditions -- -- -- -- -- -- -- -- -- -- -- Min -0.3 -0.1 -0.3 -0.1 -0.3 -0.1 -0.3 -0.1 -0.3 -0.1 -0.3 Max2 4.03, 4 0.1 3.63, 4 0.1 3.63, 4 0.1 4.03, 4 0.1 6.0 0.1 4.03, 4 Unit V V V V V V V V V V V
VDD_HV_ADR05 SR VDD_HV_ADR1 VSS_HV_ADR0 VSS_HV_ADR1 VDD_HV_ADV SR SR
MPC5643L Microcontroller Data Sheet, Rev. 6 72 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical characteristics
Table 8. Absolute maximum ratings1 (continued)
Symbol VSS_HV_ADV TVDD VIN SR SR SR Parameter 3.3 V ADC supply ground Slope characteristics on all VDD during power up Voltage on any pin with respect to ground (VSS_HV_IOx) Injected input current on any pin during overload condition Absolute sum of all injected input currents during overload condition Storage temperature Conditions -- -- -- Relative to VDD -- -- -- Min -0.1 0.5 -0.3 -0.3 -10 -50 -55 Max2 0.1 106 Unit V
3.0 x V/s (3.0 V/sec) 6.0 VDD + 0.36 10 50 150 mA mA C V
IINJPAD IINJSUM TSTG
1
SR SR SR
2 3 4 5 6
Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress have not yet been determined. 5.3 V for 10 hours cumulative over lifetime of device, 3.3 V +10% for time remaining. Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance. VDD_HV_ADR0 and VDD_HV_ADR1 cannot be operated be operated at different voltages, and need to be supplied by the same voltage source. Only when VDD < 5.2 V.
3.3
Recommended operating conditions
Table 9. Recommended operating conditions (3.3 V)
Symbol VDD_HV_REG VSS_HV_REG VDD_HV_IOx VSS_HV_IOx VDD_HV_FLA VSS_HV_FLA VDD_HV_OSC VSS_HV_OSC VDD_HV_ADR02 VDD_HV_ADR1 VDD_HV_ADV VSS_HV_AD0 VSS_HV_AD1 VSS_HV_ADV VDD_LV_REGCOR3 Parameter SR 3.3 V voltage regulator supply voltage SR 3.3 V voltage regulator reference voltage SR 3.3 V input/output supply voltage SR Input/output ground voltage SR 3.3 V flash supply voltage SR Flash memory ground SR 3.3 V crystal oscillator amplifier supply voltage SR 3.3 V crystal oscillator amplifier reference voltage SR 3.3 V / 5.0 V ADC_0 high reference voltage 3.3 V / 5.0 V ADC_1 high reference voltage SR 3.3 V ADC supply voltage SR ADC_0 ground and low reference voltage ADC_1 ground and low reference voltage SR 3.3 V ADC supply ground SR Internal supply voltage Conditions -- -- -- -- -- -- -- -- -- -- -- -- -- Min 3.0 0 3.0 0 3.0 0 3.0 0 Max1 3.6 0 3.6 0 3.6 0 3.6 0 Unit V V V V V V V V V V V V V
4.5 to 5.5 or 3.0 to 3.6 3.0 0 0 -- 3.6 0 0 --
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 73
Electrical characteristics
Table 9. Recommended operating conditions (3.3 V) (continued)
Symbol Parameter Conditions -- -- -- -- -- fCPU 120 MHz -- Min 0 -- 0 -- 0 -40 -40 Max1 0 -- 0 -- 0 125 150 Unit V V V V V C C
VSS_LV_REGCOR4 SR Internal reference voltage VDD_LV_CORx
2
SR Internal supply voltage SR Internal reference voltage SR Internal supply voltage SR Internal reference voltage SR Ambient temperature under bias SR Junction temperature under bias
VSS_LV_CORx3 VDD_LV_PLL2 VSS_LV_PLL TA TJ
1 3
Full functionality cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed. 2V DD_HV_ADR0 and VDD_HV_ADR1 cannot be operated at different voltages, and need to be supplied by the same voltage source. 3 Can be connected to emitter of external NPN. Low voltage supplies are not under user control. They are produced by an on-chip voltage regulator. 4 For the device to function properly, the low voltage grounds (V SS_LV_xxx) must be shorted to high voltage grounds (VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected to the external ballast emitter, if one is used.
3.4
Thermal characteristics
Table 10. Thermal characteristics for 144 LQFP package1
Symbol RJA D Parameter Conditions Value Unit 42 34 34 28 22 8 3 C/W C/W C/W C/W C/W
Thermal resistance, junction-to-ambient natural Single layer board - 1s convection2 Four layer board - 2s2p Thermal resistance, junction-to-ambient forced Single layer board - 1s convection at 200 ft/min Four layer board - 2s2p Thermal resistance junction-to-board3 Thermal resistance junction-to-case Junction-to-package-top natural
4
RJMA
D
RJB RJC JT
1 2
D D D
-- -- --
convection5
Thermal characteristics are targets based on simulation that are subject to change per device characterization. Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. 3 Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. 4 Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. 5 Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
MPC5643L Microcontroller Data Sheet, Rev. 6 74 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical characteristics
Table 11. Thermal characteristics for 257 MAPBGA package1
Symbol RJA D Parameter Conditions Value Unit 46 26 37 22 13 8 2 C/W C/W C/W C/W C/W
Thermal resistance junction-to-ambient natural Single layer board - 1s convection2 Four layer board - 2s2p Thermal resistance, junction-to-ambient forced Single layer board - 1s convection at 200 ft/min Four layer board - 2s2p Thermal resistance junction-to-board3 Thermal resistance junction-to-case4 Junction-to-package-top natural convection
5
RJMA
D
RJB RJC JT
1 2
D D D
-- -- --
Thermal characteristics are targets based on simulation that are subject to change per device characterization. Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. 3 Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. 4 Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. 5 Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
3.4.1
General notes for specifications at maximum junction temperature
TJ = TA + (RJA x PD) where: TA = ambient temperature for the package (oC) RJA = junction to ambient thermal resistance (oC/W) PD = power dissipation in the package (W) Eqn. 1
An estimation of the chip junction temperature, TJ, can be obtained from Equation 1:
The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. When a heat sink is used, the thermal resistance is expressed in Equation 2 as the sum of a junction to case thermal resistance and a case to ambient thermal resistance:
RJA = RJC + RCA
where: RJA = junction to ambient thermal resistance (C/W) RJC = junction to case thermal resistance (C/W) RCA = case to ambient thermal resistance (C/W)
Eqn. 2
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 75
Electrical characteristics
RJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal Characterization Parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using Equation 3: TJ = TT + (JT x PD) where: TT = thermocouple temperature on top of the package (C) JT = thermal characterization parameter (C/W) PD = power dissipation in the package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. Eqn. 3
3.4.1.1
References
Semiconductor Equipment and Materials International 3081 Zanker Road San Jose, CA 95134 USA (408) 943-6900 MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956. JEDEC specifications are available on the WEB at http://www.jedec.org. 1. 2. 3. C.E. Triplett and B. Joiner, "An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module," Proceedings of SemiTherm, San Diego, 1998, pp. 47-54. G. Kromann, S. Shidore, and S. Addison, "Thermal Modeling of a PBGA for Air-Cooled Applications," Electronic Packaging and Production, pp. 53-58, March 1998. B. Joiner and V. Adams, "Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling," Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.
3.5
* * *
Electromagnetic Interference (EMI) characteristics (cut1)
Device configuration, tet conditions, and EM testing per standard IEC61967-2 Supply voltage of 3.3 V DC Ambient temperature of 25 C
The characteristics in Table 13 were measured using:
The configuration information referenced in Table 13 is explained in Table 12.
MPC5643L Microcontroller Data Sheet, Rev. 6 76 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical characteristics
Table 12. EMI configuration summary
Configuration name Configuration A * * * * * * * * * * Description High emission = all pads have max slew rate, LVDS pads running at 40 MHz Oscillator frequency = 40 MHz System bus frequency = 80 MHz No PLL frequency modulation IEC level I ( 36 dBV) Reference emission = pads use min, mid and max slew rates, LVDS pads disabled Oscillator frequency = 40 MHz System bus frequency = 80 MHz 2% PLL frequency modulation IEC level K( 30 dBV)
Configuration B
Table 13. EMI emission testing specifications
Symbol VEME Parameter Conditions Configuration A; frequency range 150 kHz-50 MHz Configuration A; frequency range 50-150 MHz Configuration A; frequency range 150-500 MHz Configuration A; frequency range 500-1000 MHz Configuration B; frequency range 50-150 MHz Configuration B; frequency range 50-150 MHz Configuration B; frequency range 150-500 MHz Configuration B; frequency range 500-1000 MHz Min -- -- -- -- -- -- -- -- Typ 16 16 32 25 15 21 30 24 Max -- -- -- -- -- -- -- -- Unit dBV
CC Radiated emissions
3.6
Electrostatic discharge (ESD) characteristics
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts x (n + 1) supply pin). This test conforms to the AEC-Q100-002/-003/-011 standard.
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 77
Electrical characteristics
Table 14. ESD ratings1, 2
No. 1 2 3 Symbol VESD(HBM) VESD(MM) VESD(CDM) Parameter SR Electrostatic discharge (Human Body Model) SR Electrostatic discharge (Machine Model) Conditions TA = 25 C conforming to AEC-Q100-002 TA = 25 C conforming to AEC-Q100-003 Class H1C M2 C3A Max value3 2000 200 500 750 (corners) Unit V V V
SR Electrostatic discharge TA = 25 C (Charged Device Model) conforming to AEC-Q100-011
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2 A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. 3 Data based on characterization results, not tested in production.
1
3.7
* *
Static latch-up (LU)
A supply overvoltage is applied to each power supply pin. A current injection is applied to each input, output and configurable I/O pin. Table 15. Latch-up results
No. 1 Symbol LU SR Parameter Static latch-up class Conditions TA = 125 C conforming to JESD 78 Class II level A
Two complementary static tests are required on six parts to assess the latch-up performance:
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
3.8
* * * * * * * * * *
Voltage regulator electrical characteristics
High power regulator HPREG1 (internal ballast to support core current) High power regulator HPREG2 (external NPN to support core current) Low voltage detector (LVD_MAIN_1) for 3.3 V supply to IO (VDDIO) Low voltage detector (LVD_MAIN_2) for 3.3 V supply (VDDREG) Low voltage detector (LVD_MAIN_3) for 3.3 V flash supply (VDDFLASH) Low voltage detector (LVD_DIG_MAIN) for 1.2 V digital core supply (HPVDD) Low voltage detector (LVD_DIG_BKUP) for the self-test of LVD_DIG_MAIN High voltage detector (HVD_DIG_MAIN) for 1.2 V digital CORE supply (HPVDD) High voltage detector (HVD_DIG_BKUP) for the self-test of HVD_DIG_MAIN. Power on Reset (POR)
The voltage regulator is composed of the following blocks:
HPREG1 uses an internal ballast to support the core current. HPREG2 is used only when external NPN transistor is present on board to supply core current. The MPC5643L always powers up using HPREG1 if an external NPN transistor is present. Then the MPC5643L makes a transition from HPREG1 to HPREG2. This transition is dynamic. Once HPREG2 is fully operational, the controller part of HPREG1 is switched off. The following bipolar transistors are supported: * BCP68 from ON Semiconductor
MPC5643L Microcontroller Data Sheet, Rev. 6 78 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical characteristics
*
BCX68 from Infineon Table 16. Voltage regulator electrical specifications
Symbol SR Parameter External decoupling/ stability capacitor Conditions Min, max values shall be granted with respect to tolerance, voltage, temperature, and aging variations. -- -- Min 12 Typ -- Max 40 Unit F
SR SR
Combined ESR of external capacitor Number of pins for external decoupling/ stability capacitor Total capacitance on 1.2 V pins
0.01 5
-- --
0.10 --
--
CV1V2
SR
Ceramic capacitors, taking into account tolerance, aging, voltage and temperature variation Cload = 10 F x 4 --
--
--
300
nF
tSU --
Start-up time after main supply stabilization Main High Voltage Power Low Voltage Detection, upper threshold D D Main supply low voltage detector, lower threshold Digital supply high voltage detector upper threshold
-- --
-- --
2.5 2.9
ms V
-- --
-- Before a destructive reset initialization phase completion After a destructive reset initialization phase completion
2.6 Cut2: 1.355
-- --
-- Cut1: 1.5 Cut2: 1.495 Cut1: 1.4 Cut2: 1.47 Cut1: 1.4 Cut2: 1.455 Cut2: 1.43
V V
Cut1: 1.32 Cut2: 1.43 Cut1: 1.330 Cut2: 1.315 Cut2: 1.39
--
--
D
Digital supply high voltage detector lower threshold
Before a destructive reset initialization phase completion After a destructive reset initialization phase completion
--
V
--
--
D
Digital supply low voltage detector lower threshold Digital supply low voltage detector upper threshold POR rising/ falling supply threshold voltage
After a destructive reset initialization phase completion After a destructive reset initialization phase completion --
1.080
--
Cut1: 1.110 Cut2: 1.12 Cut1: 1.19 Cut2: 1.20 2.6
V
--
D
Cut1: 1.17 Cut2: 1.16 1.6
--
V
--
D
--
V
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 79
Electrical characteristics
Table 16. Voltage regulator electrical specifications (continued)
Symbol -- -- SR D Parameter Supply ramp rate LVD_MAIN: Time constant of RC filter at LVD input HVD_DIG: Time constant of RC filter at LVD input LVD_DIG: Time constant of RC filter at LVD input Conditions -- 3.3V noise rejection at the input of LVD comparator 1.2V noise rejection at the input of LVD comparator 1.2V noise rejection at the input of LVD comparator Min 3 1.1 Typ -- -- Max 0.5 x106 -- Unit V/s s
--
D
0.1
--
--
s
--
D
0.1
--
--
s
VDD
BCRTL
BCP68 V1V2 ring on board
Rb Rs Cint
Lb ESR Cv1v2 Cext
V1V2 pin MPC5643L
Figure 4. BCP68 board schematic example
NOTE
The combined ESR of the capacitors used on 1.2 V pins (V1V2 in the picture) shall be in the range of 30 m to 150 m. The minimum value of the ESR is constrained by the resonance caused by the external components, bonding inductance, and internal decoupling. The minimum ESR is required to avoid the resonance and make the regulator stable.
MPC5643L Microcontroller Data Sheet, Rev. 6 80 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical characteristics
3.9
DC electrical characteristics
Table 17. DC electrical characteristics1
Table 17 gives the DC electrical characteristics at 3.3 V (3.0 V < VDD_HV_IOx < 3.6 V).
Symbol VIL VIL VIH VIH VHYS VOL_S VOH_S VOL_M VOH_M VOL_F VOH_F VOL_SYM VOH_SYM IINJ IPU
Parameter D Minimum low level input voltage P Maximum level input voltage P Minimum high level input voltage D Maximum high level input voltage T Schmitt trigger hysteresis P Slow, low level output voltage P Slow, high level output voltage P Medium, low level output voltage P Medium, high level output voltage P Fast, high level output voltage P Fast, high level output voltage P Symmetric, high level output voltage P Symmetric, high level output voltage T DC injection current per pin P Equivalent pull-up current
Conditions -- -- -- -- -- IOL = 1.5 mA
Min -0.12 -- 0.65 VDD_HV_IOx -- 0.1 VDD_HV_IOx --
Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max -- 0.35 VDD_HV_IOx -- VDD_HV_IOx + 0.1 -- 0.5 -- 0.5 -- 0.5 -- 0.5 -- 1 -- -10 -- 130 1 0.5 1 0.35 VDD_HV_IOx VDD_HV_IOx+0.12 -- 0.5 -- 130
2
Unit V V V V V V V V V V V V V mA A
IOH = -1.5 mA VDD_HV_IOx - 0.8 IOL = 2 mA IOH = -2 mA IOL = 1.5 mA -- VDD_HV_IOx - 0.8 --
IOH = -1.5 mA VDD_HV_IOx - 0.8 IOL = 1.5 mA --
IOH = -1.5 mA VDD_HV_IOx - 0.8 -- VIN = VIL VIN = VIH -1 -130 -- 10 -- -1 -0.5 -1 -- -- -- IOL = 2 mA VIN = VIL VIN = VIH -0.12 0.65 VDD_HV_IOx 0.1 VDD_HV_IOx -- 10 --
IPD
P Equivalent pull-down current
VIN = VIL VIN = VIH
A
IIL
P Input leakage current (all bidirectional ports) Input leakage current (all ADC input-only ports) Input leakage current (shared ADC input-only ports)
TJ = -40 to +150 C
A
VILR VIHR VHYSR VOLR IPD
1 2
P RESET, low level input voltage P RESET, high level input voltage D RESET, Schmitt trigger hysteresis D RESET, low level output voltage D RESET, equivalent pull-down current
V V V V A
These specifications are design targets and subject to change per device characterization. "SR" parameter values must not exceed the absolute maximum ratings shown in Table 8.
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 81
Electrical characteristics
3.10
Supply current characteristics (cut2)
Table 18. Current consumption characteristics
Current consumption data is given in Table 18. These specifications are design targets and are subject to change per device characterization.
Symbol IDD_LV_FULL + IDD_LV_PLL
Parameter T Operating current
Conditions 1.2 V supplies TJ = ambient VDD_LV_COR = 1.32 V 1.2 V supplies TJ = 150 C VDD_LV_COR = 1.32 V
Min --
Typ --
Max 50 mA+ 2.18 mA*fCPU 80 mA+ 2.50 mA*fCPU 26 mA+ 2.10 mA*fCPU 41 mA+ 2.30 mA*fCPU 279 mA+ 2.10 mA*fCPU 318 mA+ 2.30 mA*fCPU TBD
Unit mA
--
--
IDD_LV_TYP + IDD_LV_PLL
T Operating current
1.2 V supplies TJ = ambient VDD_LV_COR = 1.32 V 1.2 V supplies TJ = 150 C VDD_LV_COR = 1.32 V
--
--
mA
--
--
IDD_LV_TYP + IDD_LV_PLL1
P Operating current
1.2 V supplies TJ = ambient VDD_LV_COR = 1.32 V 1.2 V supplies TJ = 150 C VDD_LV_COR = 1.32 V
--
--
mA
--
--
IDD_LV_BIST + IDD_LV_PLL
T Operating current
1.2 V supplies during LBIST (full LBIST configuration) TJ = ambient VDD_LV_COR = 1.32 V 1.2 V supplies TJ = 150 C VDD_LV_COR = 1.32 V
--
--
mA
--
--
TBD
IDD_LV_STOP
T Operating current in VDD STOP mode T P
TJ = ambient VDD_LV_COR = 1.32 V TJ = 55 C VDD_LV_COR = 1.32 V TJ = 150 C VDD_LV_COR = 1.32 V TJ = ambient VDD_LV_COR = 1.32 V TJ = 55 C VDD_LV_COR = 1.32 V TJ = 150 C VDD_LV_COR = 1.32 V
-- -- -- -- -- --
-- -- -- -- -- --
50 57 80 58 64 72
mA
IDD_LV_HALT
T Operating current in VDD HALT mode T P
mA
MPC5643L Microcontroller Data Sheet, Rev. 6 82 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical characteristics
Table 18. Current consumption characteristics (continued)
Symbol IDD_HV_ADC2,3 Parameter T Operating current Conditions TJ = 150 C 120 MHz ADC operating at 60 MHz VDD_HV_ADC = 3.6 V TJ = 150 C 120 MHz ADC operating at 60 MHz VDD_HV_REF = 3.6 V TJ = 150 C 120 MHz ADC operating at 60 MHz VDD_HV_REF = 5.5 V IDD_HV_OSC T Operating current TJ = 150 C 3.3 V supplies 120 MHz TJ = 150 C 3.3 V supplies 120 MHz Min -- Typ -- Max 10 Unit mA
IDD_HV_AREF3
T Operating current
--
--
3
mA
--
--
5
--
--
900
A
IDD_HV_FLASH4
T Operating current
--
--
4
mA
1
Enabled Modules in 'Typical mode': FlexPWM0, ETimer0/1/2, CTU, SWG, DMA, FlexCAN0/1, LINFlex, ADC1, DSPI0/1, PIT, CRC, PLL0/1, I/O supply current excluded 2 Internal structures hold the input voltage less than VDDA + 1.0 V on all pads powered by VDDA supplies, if the maximum injection current specification is met (3 mA for all pins) and VDDA is within the operating voltage specifications. 3 This value is the total current for both ADCs. 4 VFLASH is only available in the calibration package.
3.11
Temperature sensor electrical characteristics
Table 19. Temperature sensor electrical characteristics
Symbol -- P Accuracy Parameter Conditions TJ = -40 C to TA = 25 C TJ = TA to 125 C TS D Minimum sampling period -- Min -10 -7 4 Max 10 7 -- Unit C C s
3.12
Main oscillator electrical characteristics
The device provides an oscillator/resonator driver. Figure 5 describes a simple model of the internal oscillator driver and provides an example of a connection for an oscillator or a resonator.
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 83
Electrical characteristics
EXTAL CL Crystal EXTAL RP
XTAL
DEVICE
VDD
CL
I
R EXTAL Resonator XTAL
XTAL
DEVICE
DEVICE
Figure 5. Crystal oscillator and resonator connection scheme
NOTE
XTAL/EXTAL must not be directly used to drive external circuits.
MTRANS 1
0 VXTAL VXOSCHS 90% VXOSCHSOP 10% TXOSCHSSU valid internal clock
1/fXOSCHS
Figure 6. Main oscillator electrical characteristics
MPC5643L Microcontroller Data Sheet, Rev. 6 84 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical characteristics
x
Table 20. Main oscillator electrical characteristics
Symbol fXOSCHS gmXOSCHS VXOSCHS Parameter SR Oscillator frequency P Oscillator transconductance D Oscillation amplitude Conditions1 Min -- VDD = 3.3 V 10% fOSC = 4, 8, 10, 12, 16 MHz fOSC = 40 MHz VXOSCHSOP IXOSCHS TXOSCHSSU D Oscillation operating point D Oscillator consumption T Oscillator start-up time -- -- fOSC = 4, 8, 10, 12 MHz2 fOSC = 16, 40 VIH VIL
1 2
Value Unit Typ -- -- -- -- 0.82 -- -- -- -- -- Max 40.0 13.25 -- -- -- 3.5 6 2 VDD + 0.4 0.35 x VDD V V V mA ms MHz mA/V V 4.0 4.5 1.3 1.1 -- -- -- -- 0.65 x VDD -0.4
MHz2
SR Input high level CMOS Schmitt Trigger SR Input low level CMOS Schmitt Trigger
Oscillator bypass mode Oscillator bypass mode
VDD = 3.3 V 10%, TJ = -40 to +150 C, unless otherwise specified. The recommended configuration for maximizing the oscillator margin are: XOSC_MARGIN = 0 for 4 MHz quartz XOSC_MARGIN = 1 for 8/16/40 MHz quartz
3.13
FMPLL electrical characteristics
Table 21. FMPLL electrical characteristics
Symbol Parameter Conditions Crystal reference -- -- Measured using clock division (typically 16) -- -- Lower limit Upper limit
4,5
Min 4 4 4 20 16 -- 1.6 24
Typ -- -- -- -- -- -- -- -- -- --
Max 40 16 1202 150 120 1 / fsys 3.7 56 TBD 200
Unit MHz MHz MHz MHz MHz ns MHz
fREF_CRYSTAL D FMPLL reference frequency fREF_EXT range1 fPLL_IN D Phase detector input frequency range (after pre-divider)
fFMPLLOUT D Clock frequency range in normal mode fFREE fsys tCYC fLORL fLORH fSCM tLOCK P Free running frequency D On-chip FMPLL frequency2 D System clock period D Loss of reference frequency window3 D Self-clocked mode frequency P Lock time
-- Stable oscillator (fPLLIN = 4 MHz), stable VDD
20 --
MHz s
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 85
Electrical characteristics
Table 21. FMPLL electrical characteristics (continued)
Symbol tlpll tdc CJITTER Parameter D FMPLL lock time 6, 7 D Duty cycle of reference T CLKOUT period jitter
8,9,10,11
Conditions -- -- Long-term jitter (avg. over 2 ms interval), fSYS maximum
Min -- 40 -6 -- -- -- -- -6 -18 0.25 -0.5
Typ -- -- -- -- -- -- -- -- -- -- -- --
Max 200 60 6 175 185 200 6 6 18 2.012 -8.0 100
Unit s % ns ps ps ps ns % fsys % fsys % fsys kHz
tPKJIT
T Single period jitter (peak to peak) PHI @ 120 MHz, Input clock @ 4 MHz PHI @ 100 MHz, Input clock @ 4 MHz PHI @ 80 MHz, Input clock @ 4 MHz
tLTJIT
fLCK fUL fCS fDS fMOD
1 2
T Long term jitter D Frequency LOCK range D Frequency un-LOCK range D Modulation Depth
PHI @ 16 MHz, Input clock @ 4 MHz -- -- Center spread Down Spread
D Modulation
frequency13
--
--
Considering operation with FMPLL not bypassed. With FM; the value does not include a possible +2% modulation 3 "Loss of Reference Frequency" window is the reference frequency range outside of which the FMPLL is in self clocked mode. 4 Self clocked mode frequency is the frequency that the FMPLL operates at when the reference frequency falls outside the fLOR window. 5f VCO is the frequency at the output of the VCO; its range is 256-512 MHz. fSCM is the self-clocked mode frequency (free running frequency); its range is 20-150 MHz. fSYS = fVCOODF 6 This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for this FMPLL, load capacitors should not exceed these limits. 7 This specification applies to the period required for the FMPLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). 8 This value is determined by the crystal manufacturer and board design. 9 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fSYS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FMPLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the CJITTER percentage for a given interval. 10 Proper PC board layout procedures must be followed to achieve specifications. 11 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C JITTER and either fCS or fDS (depending on whether center spread or down spread modulation is enabled). 12 This value is true when operating at frequencies above 60 MHz, otherwise f CS is 2% (above 64 MHz). 13 Modulation depth is attenuated from depth setting when operating at modulation frequencies above 50 kHz.
MPC5643L Microcontroller Data Sheet, Rev. 6 86 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical characteristics
3.14
16 MHz RC oscillator electrical characteristics
Table 22. RC oscillator electrical characteristics
Symbol fRC Parameter P RC oscillator frequency P Fast internal RC oscillator variation with respect to fRC. Conditions TJ = 25 C -- Min -- -- Typ 16 -- Max -- 5 Unit MHz %
RCMVAR
3.15
ADC electrical characteristics
Offset Error OSE Gain Error GE
4095 4094 4093 4092 4091 4090
The device provides a 12-bit Successive Approximation Register (SAR) Analog-to-Digital Converter.
( 2)
code out
7
1 LSB ideal =(VrefH-VrefL)/ 4096 = 3.3V/ 4096 = 0.806 mV Total Unadjusted Error TUE = +/- 6 LSB = +/- 4.84mV
( 1)
6 5
(5)
4
(4)
3 2 1
(3) 1 LSB (ideal)
1 2 3 4 5 6 7
(1) Example of an actual transfer curve (2) The ideal transfer curve (3) Differential non-linearity error (DNL) (4) Integral non-linearity error (INL) (5) Center of a step of the actual transfer curve
0
4089 4090 4091 4092 4093 4094 4095
Vin(A) (LSBideal)
Offset Error OSE
Figure 7. ADC characteristics and error definitions
3.15.1
Input Impedance and ADC Accuracy
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; further, it sources charge during the sampling phase, when the analog signal source is a high-impedance source. A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 87
Electrical characteristics
be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the ADC itself. In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: CS being substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path to ground. For instance, assuming a conversion rate of 1 MHz, with CS equal to 3 pF, a resistance of 330 k is obtained (REQ = 1 / (fC CS), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage partitioning between this resistance (sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit must be designed to respect the Equation 4: R S + R F + R L + R SW + R AD -1 V A -------------------------------------------------------------------------- -- LSB R EQ 2
Eqn. 4
Equation 4 generates a constraint for external network design, in particular on resistive path. Internal switch resistances (RSW and RAD) can be neglected with respect to external resistances.
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME VDD Channel Selection RSW1
Sampling
Source RS
Filter RF
Current Limiter RL
RAD
VA
CF
CP1
CP2
RS Source Impedance RF Filter Resistance CF Filter Capacitance Current Limiter Resistance RL RSW1 Channel Selection Switch Impedance RAD Sampling Switch Impedance CP Pin Capacitance (two contributions, CP1 and CP2) CS Sampling Capacitance
Figure 8. Input Equivalent Circuit A second aspect involving the capacitance network shall be considered. Assuming the three capacitances CF, CP1 and CP2 are initially charged at the source voltage VA (refer to the equivalent circuit reported in Figure 8): A charge sharing phenomenon is installed when the sampling phase is started (A/D switch close).
MPC5643L Microcontroller Data Sheet, Rev. 6 88 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical characteristics
VCS VA VA2
Voltage Transient on CS V <0.5 LSB
1 2
1 < (RSW + RAD) CS << TS
VA1
2 = RL (CS + CP1 + CP2)
TS t
Figure 9. Transient Behavior during Sampling Phase In particular two different transient periods can be distinguished: * A first and quick charge transfer from the internal capacitance CP1 and CP2 to the sampling capacitance CS occurs (CS is supposed initially completely discharged): considering a worst case (since the time constant in reality would be faster) in which CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and CS are in series, and the time constant is CP CS 1 = R SW + R AD -------------------CP + CS
Eqn. 5
Equation 5 can again be simplified considering only CS as an additional worst condition. In reality, the transient is faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time TS is always much longer than the internal time constant: 1 R SW + R AD C S T S Eqn. 6
The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the voltage VA1 on the capacitance according to Equation 7: V A1 C S + C P1 + C P2 = V A C P1 + C P2 * Eqn. 7
A second charge transfer involves also CF (that is typically bigger than the on-chip capacitance) through the resistance RL: again considering the worst case in which CP2 and CS were in parallel to CP1 (since the time constant in reality would be faster), the time constant is: 2 R L C S + C P1 + C P2 Eqn. 8
In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time TS, a constraints on RL sizing is obtained: 10 2 = 10 R L C S + C P1 + C P2 TS
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 89
Eqn. 9
Electrical characteristics
Of course, RL shall be sized also according to the current limitation constraints, in combination with RS (source impedance) and RF (filter resistance). Being CF definitively bigger than CP1, CP2 and CS, then the final voltage VA2 (at the end of the charge transfer transient) will be much higher than VA1. Equation 10 must be respected (charge balance assuming now CS already charged at VA1): VA2 C S + C P1 + C P2 + C F = V A C F + V A1 C P1 + C P2 + C S Eqn. 10
The two transients above are not influenced by the voltage source that, due to the presence of the RFCF filter, is not able to provide the extra charge to compensate the voltage drop on CS with respect to the ideal source VA; the time constant RFCF of the filter is very high with respect to the sampling time (TS). The filter is typically designed to act as anti-aliasing.
Analog Source Bandwidth (VA) Noise
TC 2 RFCF (Conversion Rate vs. Filter Pole) fF f0 (Anti-aliasing Filtering Condition) 2 f0 fC (Nyquist)
f0
f
Sampled Signal Spectrum (fC = conversion Rate)
Anti-Aliasing Filter (fF = RC Filter pole)
fF
f
f0
fC
f
Figure 10. Spectral representation of input signal Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, fF), according to the Nyquist theorem the conversion rate fC must be at least 2f0; it means that the constant time of the filter is greater than or at least equal to twice the conversion period (TC). Again the conversion period TC is longer than the sampling time TS, which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter RFCF is definitively much higher than the sampling time TS, so the charge level on CS cannot be modified by the analog signal source during the time in which the sampling switch is closed. The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage drop on CS; from the two charge balance equations above, it is simple to derive Equation 11 between the ideal and real sampled voltage on CS: Eqn. 11 VA C P1 + C P2 + C F ----------- = ------------------------------------------------------V A2 C P1 + C P2 + C F + C S From this formula, in the worst case (when VA is maximum, that is for instance 5 V), assuming to accept a maximum error of half a count, a constraint is evident on CF value: Eqn. 12 C F 2048 C S
MPC5643L Microcontroller Data Sheet, Rev. 6 90 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical characteristics
Table 23. ADC conversion characteristics
Symbol fCK Parameter SR ADC Clock frequency (depends on ADC configuration) (The duty cycle depends on AD_CK2 frequency) SR Sampling frequency D Sample time4 D Conversion time
5
Conditions1 --
Min 3
Typ Max -- 60
Unit MHz
fs tsample tconv CS6 CP16 CP26 RSW16 RAD6 INL DNL OFS GNE IS1WINJ (cut2 only)
-- 60 MHz TBD -- -- -- VREF range = 4.5 to 5.5 V VREF range = 3.0 to 3.6 V
-- 383 625 -- -- -- -- -- -- -2 -1 -6 -6
-- -- -- -- -- -- -- -- -- -- -- -- --
1.003 -- -- 7.32 5(7) 0.8 0.3 875 825 2 2 6 6
MHz ns ns pF pF pF k LSB LSB LSB LSB
D ADC input sampling capacitance D ADC input pin capacitance 1 D ADC input pin capacitance 2 D Internal resistance of analog source
D Internal resistance of analog source P Integral non linearity P Differential non T Offset error T Gain error linearity8
-- -- -- -- -- (single ADC channel)
Max leakage Max positive/negative injection
150C
-- -3
-- --
250 3
nA mA
IS1WWINJ (cut2 only)
(double ADC channel) Max leakage Max positive/negative injection 150C |Vref_ad0 - Vref_ad1| < 150mV -- -- -- -- Without current injection With current injection Without current injection With current injection -- -3.6 67 TBD 65 10.5 -6 -8 -8 -10 -- -- -- -- -- -- -- -- -- -- 300 3.6 -- -- -- -- 6 8 8 10 nA mA dB dB dB bits LSB LSB LSB LSB
SNR THD SINAD ENOB TUEIS1WINJ (cut2 only)
T Signal-to-noise ratio T Total harmonic distortion T Signal-to-noise and distortion T Effective number of bits P Total unadjusted error for IS1WINJ T
TUEIS1WWINJ P Total unadjusted error for IS1WWINJ (cut2 only) T
1 2
VDD = 3.3 V, TJ = -40 to +150 C, unless otherwise specified and analog input voltage from VAGND to VAREF. AD_CK clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC. 3 This is the maximum frequency that the analog portion of the ADC can attain. A sustained conversion at this frequency is not possible.
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 91
Electrical characteristics
4
5 6 7 8
During the sample time the input capacitance CS can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tsample. After the end of the sample time tsample, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tsample depend on programming. This parameter does not include the sample time tsample, but only the time for determining the digital result and the time to load the result register with the conversion result. See Figure 8. For the 144-pin package No missing codes
3.16
Flash memory electrical characteristics
Table 24. Flash memory program and erase electrical specifications
No. 1 2 3 4 5 6 7
1 2
Symbol
Parameter
Min Typ1 -- -- -- -- -- -- -- 39 48 TBD TBD TBD TBD TBD
Factory Initial Lifetime Unit Avg2 Max3 Max4 -- 53 TBD TBD TBD TBD TBD -- 100 500 750 900 1300 500 500 5000 5000 5000 7500 s s ms ms ms ms ms
TDWPROGRAM *5 Double word (64 bits) program time6 TPPROGRAM T16KPPERASE *5 *5 Page(128 bits) program time6
16 KB block pre-program and erase time
T48KPPERASE *5 48 KB block pre-program and erase time T64KPPERASE *5 64 KB block pre-program and erase time T128KPPERASE T256KPPERASE *5 *5 128 KB block pre-program and erase time 256 KB block pre-program and erase time
2600 15000
3 4 5 6
Typical program and erase times assume nominal supply values and operation at TJ = 25 C. These values are characterized, but not tested. Factory Average program and erase times represent the effective performance averaged over > 1024 pages or blocks, and are provided for factory throughput estimation assuming < 100 program/erase cycles, nominal supply values and operation at TJ = 25 C. These values are characterized, but not tested. Initial Max program and erase times provide guidance for time-out limits used in the factory and apply for < 100 program/erase cycles, nominal supply values and operation at TJ = 25 C. These values are verified at production test. Lifetime Max program and erase times apply across the voltage, temperature, and cycling range of product life. These values are characterized, but not tested. See Notes for individual specifications, as shown in column headings. Actual hardware programming times. These do not include software overhead.
Table 25. Flash memory timing
Value Symbol TRES TDONE Parameter Min D Time from clearing the MCR-ESUS or PSUS bit with EHV = 1 until DONE goes low D Time from 0 to 1 transition on the MCR-EHV bit initiating a program/erase until the MCR-DONE bit is cleared -- -- Typ -- -- Max 100 5 ns ns Unit
MPC5643L Microcontroller Data Sheet, Rev. 6 92 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical characteristics
Table 26. Flash memory module life
Value No. 1 2 3 Symbol P/E P/E Parameter Min C Number of program/erase cycles per block for 16 KB, 48 KB, 100000 and 64 KB blocks over the operating temperature range1 C Number of program/erase cycles per block for 128 KB and 256 KB blocks over the operating temperature range1 1000 Typ -- 1000002 Max -- -- cycles cycles years 20 10 5 -- -- -- -- -- -- Unit
Retention C Minimum data retention at 85 C average ambient temperature3 Blocks with 0-1,000 P/E cycles Blocks with 1,001-10,000 P/E cycles Blocks with 10,001-100,000 P/E cycles
Operating temperature range is TJ from -40 C to 150 C. Typical endurance is evaluated at 25 C. Product qualification is performed to the minimum specification. For additional information on the Freescale definition of Typical Endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory. 2 Typical P/E cycles is 100,000 cycles for 128 KB and 256 KB blocks. For additional information on the Freescale definition of Typical Endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory. 3 Ambient temperature averaged over duration of application, not to exceed product operating temperature range.
1
3.17
SWG electrical characteristics
Table 27. SWG electrical characteristics
Symbol SINAD D Parameter Signal-to-noise ratio plus distortion Min 50 Max -- Unit dB
3.18
3.18.1
AC specifications
Pad AC specifications
Table 28. Pad AC specifications (3.3 V , IPP_HVE = 0 )1
Tswitchon1 (ns) Min Typ -- -- -- -- Max 40 40 40 40 Rise/Fall2 (ns) Min -- -- -- -- Typ -- -- -- -- Max 40 50 75 100 Frequency (MHz) Min -- -- -- -- Typ -- -- -- -- Max 4 2 2 2 Current slew3 (mA/ns) Min 0.01 0.01 0.01 0.01 Typ -- -- -- -- Max 2 2 2 2 25 50 100 200 Load drive (pF)
No.
Pad
1
Slow
T
3 3 3 3
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 93
Electrical characteristics
Table 28. Pad AC specifications (3.3 V , IPP_HVE = 0 )1 (continued)
Tswitchon1 (ns) Min 2 Medium T 1 1 1 1 3 Fast T 1 1 1 1 4 5
1 2
No.
Pad
Rise/Fall2 (ns) Min -- -- -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- Max 12 25 40 70 4 7 12 18 5 TBD
Frequency (MHz) Min -- -- -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- Max 40 20 13 7 72 55 40 25 50 --
Current slew3 (mA/ns) Min 2.5 2.5 2.5 2.5 3 7 7 7 3 -- Typ -- -- -- -- -- -- -- -- -- -- Max 7 7 7 7 40 40 40 40 25 --
Load drive (pF) 25 50 100 200 25 50 100 200 25 50
Typ -- -- -- -- -- -- -- -- -- --
Max 15 15 15 15 6 6 6 6 8 --
Symmetric Pull Up/Down (3.6 V max)
T D
1 --
Propagation delay from VDD_HV_IOx/2 of internal signal to Pchannel/Nchannel switch-on condition. Slope at rising/falling edge. 3 Data based on characterization results, not tested in production.
VDDE/2 Pad Data Input
Rising Edge Output Delay
Falling Edge Output Delay VOH
Pad Output
VOL
Figure 11. Pad output delay
3.19
Reset sequence
This section shows the duration for different reset sequences. It describes the different reset sequences and it specifies the start conditions and the end indication for the reset sequences.
MPC5643L Microcontroller Data Sheet, Rev. 6 94 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical characteristics
3.19.1
Reset sequence duration
Table 29 specifies the minimum and the maximum reset sequence duration for the five different reset sequences described in Section 3.19.2, Reset sequence description. Table 29. RESET sequences
TReset No. Symbol Parameter Conditions Min 1 TDRB CC Destructive Reset Sequence, BIST enabled cut1 cut2 2 3 TDR TERLB CC CC Destructive Reset Sequence, BIST disabled External Reset Sequence Long, BIST enabled -- cut1 cut2 4 5
1
Unit Typ 60 47 4200 57 45 150 4 Max1 65 51 5000 65 49 400 10 ms ms s ms ms s s
52 40 500 52 41 35 1
TFRL TFRS
CC CC
Functional Reset Sequence Long Functional Reset Sequence Short
-- --
The maximum value is applicable only if the reset sequence duration is not prolonged by an extended assertion of RESET by an external reset generator.
3.19.2
Reset sequence description
The figures in this section show the internal states of the chip during the five different reset sequences. The doted lines in the figures indicate the starting point and the end point for which the duration is specified in Table 29. The start point and end point conditions as well as the reset trigger mapping to the different reset sequences is specified in Section 3.19.3, Reset sequence trigger mapping. With the beginning of DRUN mode the first instruction is fetched and executed. At this point application execution starts and the internal reset sequence is finished. The figures below show the internal states of the chip during the execution of the reset sequence and the possible states of the signal pin RESET.
NOTE
RESET is a bidirectional pin. The voltage level on this pin can either be driven low by an external reset generator or by the chip internal reset circuitry. A high level on this pin can only be generated by an external pull up resistor which is strong enough to overdrive the weak internal pull down resistor. The rising edge on RESET in the following figures indicates the time when the device stops driving it low. The reset sequence durations given in table Table 29 are applicable only if the internal reset sequence is not prolonged by an external reset generator keeping RESET asserted low beyond the last PHASE3.
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 95
Electrical characteristics
Reset Sequence Trigger Reset Sequence Start Condition
RESET RESET_B
PHASE0
Establish IRC and PWR
PHASE1,2
PHASE3
Device Self Test Setup
BIST
PHASE1,2
PHASE3
Device
DRUN
Application Execution
Flash init
Config
MBIST
LBIST
Flash init
Config
TDRB, min < TReset < TDRB, max
Figure 12. Destructive Reset Sequence, BIST enabled
Reset Sequence Trigger Reset Sequence Start Condition
RESET_B RESET PHASE0
Establish IRC and PWR Flash init
PHASE1,2
PHASE3
Device Config
DRUN
Application Execution
TDR, min < TReset < TDR, max
Figure 13. Destructive Reset Sequence, BIST disabled
Reset Sequence Trigger Reset Sequence Start Condition
RESET RESET_B
PHASE1,2
PHASE3
Device Self Test Setup
BIST
PHASE1,2
PHASE3
Device
DRUN
Application Execution
Flash init
Config
MBIST
LBIST
Flash init
Config
TERLB, min < TReset < TERLB, max
Figure 14. External Reset Sequence Long, BIST enabled
MPC5643L Microcontroller Data Sheet, Rev. 6 96 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical characteristics
Reset Sequence Trigger Reset Sequence Start Condition
RESET_B RESET PHASE1,2 PHASE3
Device Flash init Config
DRUN
Application Execution
TFRL, min < TReset < TFRL, max
Figure 15. Functional Reset Sequence Long
Reset Sequence Trigger Reset Sequence Start Condition
RESET_B RESET PHASE3 DRUN
Application Execution
TFRS, min < TReset < TFRS, max
Figure 16. Functional Reset Sequence Short The reset sequences shown in Figure 15 and Figure 16 are triggered by functional reset events. RESET is driven low during these two reset sequences only if the corresponding functional reset source (which triggered the reset sequence) was enabled to drive RESET low for the duration of the internal reset sequence1.
3.19.3
Reset sequence trigger mapping
The following table shows the possible trigger events for the different reset sequences. It specifies the reset sequence start conditions as well as the reset sequence end indications that are the basis for the timing data provided in Table 29.
1.See RGM_FBRE register for more details.
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 97
Electrical characteristics
Table 30. Reset sequence trigger -- reset sequence
Reset Sequence Reset Sequence Trigger Reset Sequence Start Condition Reset Sequence End Indication Destructiv e Reset Sequence, BIST enabled1 Destructiv e Reset Sequence, BIST disabled1 External Reset Sequenc e Long, BIST enabled cannot trigger Functiona l Reset Sequenc e Long Functiona l Reset Sequenc e Short
All internal destructive reset sources (LVDs or internal HVD during power-up and during operation) Assertion of RESET3
Section 3.1 9.4.1, Destructive reset
Release of RESET2
triggers
cannot trigger
cannot trigger
Section 3.1 9.4.2, External reset via RESET Sequence starts with internal reset trigger Release of RESET7
cannot trigger
triggers4
triggers5
triggers6
All internal functional reset sources configured for long reset All internal functional reset sources configured for short reset
1 2
cannot trigger
cannot trigger
triggers
cannot trigger
cannot trigger
cannot trigger
cannot trigger
triggers
3
4 5 6 7
Whether BIST is executed or not depends on the chip configuration data stored in the shadow sector of the NVM. End of the internal reset sequence (as specified in Table 29) can only be observed by release of RESET if it is not held low externally beyond the end of the internal sequence which would prolong the internal reset PHASE3 till RESET is released externally. The assertion of RESET can only trigger a reset sequence if the device was running (RESET released) before. RESET does not gate a Destructive Reset Sequence, BIST enabled or a Destructive Reset Sequence, BIST disabled. However, it can prolong these sequences if RESET is held low externally beyond the end of the internal sequence (beyond PHASE3). If RESET is configured for long reset (default) and if BIST is enabled via chip configuration data stored in the shadow sector of the NVM. If RESET is configured for long reset (default) and if BIST is disabled via chip configuration data stored in the shadow sector of the NVM. If RESET is configured for short reset Internal reset sequence can only be observed by state of RESET if bidirectional RESET functionality is enabled for the functional reset source which triggered the reset sequence.
MPC5643L Microcontroller Data Sheet, Rev. 6 98 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical characteristics
3.19.4
Reset sequence -- start condition
The impact of the voltage thresholds on the starting point of the internal reset sequence are becoming important if the voltage rails / signals ramp up with a very slow slew rate compared to the overall reset sequence duration.
3.19.4.1
Destructive reset
Figure 17 shows the voltage threshold that determines the start of the Destructive Reset Sequence, BIST enabled and the start for the Destructive Reset Sequence, BIST disabled.
V Supply Rail Vmax Vmin
TReset, max starts here
t
TReset, min starts here
Figure 17. Reset sequence start for Destructive Resets Table 31. Voltage Thresholds
Variable name Vmin Vmax Supply Rail Value Refer to Table 16 Refer to Table 16 VDD_HV_PMU
3.19.4.2
External reset via RESET
Figure 18 shows the voltage thresholds that determine the start of the reset sequences initiated by the assertion of RESET as specified in Table 30.
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 99
Electrical characteristics
V RESET_B RESET
0.65 * VDD_HV_IO 0.35 * VDD_HV_IO
TReset, max starts here
t
TReset, min starts here
Figure 18. Reset sequence start via RESET assertion
3.19.5
External watchdog window
If the application design requires the use of an external watchdog the data provided in Section 3.19, Reset sequence can be used to determine the correct positioning of the trigger window for the external watchdog. Figure 19 shows the relationships between the minimum and the maximum duration of a given reset sequence and the position of an external watchdog trigger window.
Watchdog needs to be triggered within this window
TWDStart, min
External Watchdog Window Closed
External Watchdog Window Open
TWDStart, max
External Watchdog Window Closed External Watchdog Window Open
Watchdog trigger
TReset, min
Basic Application Init Application Running
TReset, max
Basic Application Init Application Running
Earliest Application Start Internal Reset Sequence
Start condition (signal or voltage rail)
Latest Application Start
Application time required to prepare watchdog trigger
Figure 19. Reset sequence - External watchdog trigger window position
3.20
AC timing characteristics
AC Test Timing Conditions: Unless otherwise noted, all test conditions are as follows: * TJ = -40 to 150 C * Supply voltages as specified in Table 9
MPC5643L Microcontroller Data Sheet, Rev. 6 100 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical characteristics
* Input conditions: All Inputs: tr, tf = 1 ns * Output Loading: All Outputs: 50 pF
3.20.1
RESET pin characteristics
VDD VDDMIN
The MPC5643L implements a dedicated bidirectional RESET pin.
RESET
VIH VIL device reset forced by RESET device start-up phase
Figure 20. Start-up reset requirements
VRESET hw_rst
VDD
`1'
VIH
VIL
`0'
filtered by hysteresis filtered by lowpass filter WFRST filtered by lowpass filter WFRST WNFRST unknown reset state device under hardware reset
Figure 21. Noise filtering on reset signal
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 101
Electrical characteristics
Table 32. RESET electrical characteristics
No. 1 Symbol Ttr Parameter
2
Conditions1 CL = 25pF CL = 50pF CL = 100pF
Min -- -- -- -- 500
Typ -- -- -- -- --
Max 12 25 40 40 --
Unit ns
D Output transition time output pin
2 3
1 2
WFRST
P nRESET input filtered pulse
-- --
ns ns
WNFRST P nRESET input not filtered pulse
VDD = 3.3 V 10%, TJ = -40 to +150 C, unless otherwise specified CL includes device and package capacitance (CPKG < 5 pF).
3.20.2
WKUP/NMI timing
Table 33. WKUP/NMI glitch filter
No. 1 2 Symbol WFNMI Parameter Min -- 205 Typ -- -- Max 45 -- Unit ns ns
D NMI pulse width that is rejected
WNFNMI D NMI pulse width that is passed
3.20.3
No. 1 2 3 4 5 6 7 8 11 12 13 14 15
IEEE 1149.1 JTAG interface timing
Table 34. JTAG pin AC electrical characteristics
Symbol tJCYC tJDC tTCKRISE tTMSS, tTDIS D TCK cycle time D TCK clock pulse width (measured at VDDE/2) D TCK rise and fall times (40%-70%) D TMS, TDI data setup time Parameter Conditions -- -- -- -- -- -- -- -- -- -- -- -- -- Min Max Unit 100 40 -- 5 25 -- 0 -- -- -- -- 50 50 -- 60 3 -- -- 20 -- 20 50 50 50 -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns
tTMSH, tTDIH D TMS, TDI data hold time tTDOV tTDOI tTDOHZ tBSDV tBSDVZ tBSDHZ tBSDST tBSDHT D TCK low to TDO data valid D TCK low to TDO data invalid D TCK low to TDO high impedance D TCK falling edge to output valid D TCK falling edge to output valid out of high impedance D TCK falling edge to output high impedance D Boundary scan input valid to TCK rising edge D TCK rising edge to boundary scan input invalid
MPC5643L Microcontroller Data Sheet, Rev. 6 102 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical characteristics
TCK 2 3 1 3 2
Figure 22. JTAG test clock input timing
TCK
4 5
TMS, TDI
6 7 8
TDO
Figure 23. JTAG test access port timing
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 103
Electrical characteristics
TCK 11 13
Output Signals
12
Output Signals 14 15
Input Signals
Figure 24. JTAG boundary scan timing
3.20.4
No. 1 2 3 4 5 6 7 8 9 10
1
Nexus timing
Table 35. Nexus debug port timing1
Symbol tMCYC tMDC tMDOV tEVTIPW tEVTOPW tTCYC tTDC D MCKO Cycle Time D MCKO Duty Cycle D MCKO Low to MDO, MSEO, EVTO Data D EVTI Pulse Width D EVTO Pulse Width D TCK Cycle Time D TCK Duty Cycle
3
Parameter
Conditions Min -- -- Valid2 -- -- -- -- -- -- 15.6 40 -0.1 4.0 1 40 40 8 5 0
Max -- 60
Unit ns %
0.25 tMCYC -- tTCYC tMCYC -- 60 -- -- 25 ns % ns ns ns
tNTDIS, tNTMSS D TDI, TMS Data Setup Time tNTDIH, tNTMSH D TDI, TMS Data Hold Time tJOV D TCK Low to TDO Data Valid
JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. 2 For all Nexus modes except DDR mode, MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
MPC5643L Microcontroller Data Sheet, Rev. 6 104 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical characteristics
3
The system clock frequency needs to be four times faster than the TCK frequency.
1 2 MCKO
3
MDO MSEO EVTO Output Data Valid
5
EVTI
4
Figure 25. Nexus output timing
MCKO
MDO, MSEO
MDO/MSEO data are valid during MCKO rising and falling edge
Figure 26. Nexus DDR Mode output timing
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 105
Electrical characteristics
6
7
TCK
8 9
TMS, TDI
10
TDO
Figure 27. Nexus TDI, TMS, TDO timing
3.20.5
No. 1 2 3
1
External interrupt timing (IRQ pin)
Table 36. External interrupt timing
Symbol tIPWL tIPWH tICYC Parameter D IRQ pulse width low D IRQ pulse width high D IRQ edge to edge time1 Conditions -- -- -- Min Max Unit 3 3 6 -- -- -- tCYC tCYC tCYC
Applies when IRQ pins are configured for rising edge or falling edge events, but not both.
MPC5643L Microcontroller Data Sheet, Rev. 6 106 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical characteristics
IRQ
1 2 3
Figure 28. External interrupt timing
3.20.6
No. 1
DSPI timing
Table 37. DSPI timing
Symbol tSCK D D D Parameter DSPI cycle time Conditions Master (MTFE = 0) Slave (MTFE = 0) Slave Receive Only PCS to SCK delay After SCK delay SCK duty cycle Slave access time Slave SOUT disable time PCSx to PCSS time PCSS to PCSx time Data setup time for inputs -- -- -- SS active to SOUT valid SS inactive to SOUT High-Z or invalid -- -- Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) Mode1 Min 62 62 16 16 16 Max -- -- -- -- -- ns ns ns ns ns ns ns ns Unit ns
2 3 4 5 6 7 8 9
tCSC tASC tSDC tA tDIS tPCSC tPASC tSUI
D D D D D D D D
tSCK/2 - 10 tSCK/2 + 10 -- -- 13 13 20 2 5 20 -5 4 11 -5 -- -- -- -- 40 10 -- -- -- -- -- -- -- -- -- -- 4 23 12 4
10
tHI
D
Data hold time for inputs
Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1)
ns
11
tSUO
D
Data valid (after SCK edge)
Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1)
ns
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 107
Electrical characteristics
Table 37. DSPI timing (continued)
No. 12 Symbol tHO D Parameter Data hold time for outputs Conditions Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) 13
1
Min -2 6 6 -2 --
Max -- -- -- -- 4
Unit ns
fmax
D
Maximum DSPI speed
--
MHz
Slave Receive Only Mode can operate at a maximum frequency of 60 MHz. In this mode, the DSPI can receive data on SIN, but no valid data is transmitted on SOUT.
2 PCSx 4 SCK Output (CPOL=0) 4 1
3
SCK Output (CPOL=1) 9 SIN 10 Data 12 SOUT First Data Data Last Data 11 Last Data
First Data
Note: The numbers shown are referenced in Table 37.
Figure 29. DSPI classic SPI timing -- master, CPHA = 0
MPC5643L Microcontroller Data Sheet, Rev. 6 108 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical characteristics
PCSx
SCK Output (CPOL=0) 10 SCK Output (CPOL=1) 9 SIN First Data 12 SOUT First Data Data Data Last Data 11 Last Data
Note: The numbers shown are referenced in Table 37.
Figure 30. DSPI classic SPI timing -- master, CPHA = 1
3
2 SS 1 SCK Input (CPOL=0) 4 SCK Input (CPOL=1) 5 SOUT First Data 9 SIN 10 Data 12 Data 11 4
6
Last Data
First Data
Last Data
Note: The numbers shown are referenced in Table 37.
Figure 31. DSPI classic SPI timing -- slave, CPHA = 0
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 109
Electrical characteristics
SS
SCK Input (CPOL=0)
SCK Input (CPOL=1) 5 SOUT
11 12 First Data 9 10 Data Last Data Data Last Data 6
SIN
First Data
Note: The numbers shown are referenced in Table 37.
Figure 32. DSPI classic SPI timing -- slave, CPHA = 1
3 PCSx 4 2 SCK Output (CPOL=0) SCK Output (CPOL=1) 9 SIN First Data 12 SOUT First Data Data Data 11 Last Data Last Data 4 1
10
Note: The numbers shown are referenced in Table 37.
Figure 33. DSPI modified transfer format timing -- master, CPHA = 0
MPC5643L Microcontroller Data Sheet, Rev. 6 110 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical characteristics
PCSx
SCK Output (CPOL=0)
SCK Output (CPOL=1) 9 SIN First Data Data 12 SOUT First Data Data 10
Last Data 11 Last Data
Note: The numbers shown are referenced in Table 37.
Figure 34. DSPI modified transfer format timing -- master, CPHA = 1
3
SS
2 1
SCK Input (CPOL=0) 4 SCK Input (CPOL=1) 5 SOUT First Data 9 SIN First Data Data Data 11 12 Last Data 10 Last Data 6 4
Note: The numbers shown are referenced in Table 37.
Figure 35. DSPI modified transfer format timing - slave, CPHA = 0
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 111
Package characteristics
SS
SCK Input (CPOL=0)
SCK Input (CPOL=1) 5 SOUT
11 12 First Data 9 10 Data Last Data Data Last Data 6
SIN
First Data
Note: The numbers shown are referenced in Table 37.
Figure 36. DSPI modified transfer format timing -- slave, CPHA = 1
7 PCSS PCSx Note: The numbers shown are referenced in Table 37.
8
Figure 37. DSPI PCS strobe (PCSS) timing
4
4.1
Package characteristics
Package mechanical data
MPC5643L Microcontroller Data Sheet, Rev. 6 112 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Package characteristics
Figure 38. 144 LQFP package mechanical drawing (1 of 2)
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 113
Package characteristics
Figure 39. 144 LQFP package mechanical drawing (2 of 2)
MPC5643L Microcontroller Data Sheet, Rev. 6 114 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Package characteristics
Figure 40. 257 MAPBGA package mechanical drawing (1 of 2)
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 115
Package characteristics
Figure 41. 257 MAPBGA package mechanical drawing (2 of 2)
MPC5643L Microcontroller Data Sheet, Rev. 6 116 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Ordering information
5
Ordering information
M PC 5643L F F0 M LQ 1
Qualification status Core code (Power Architecture) Device number F = FlexRay (blank) = No FlexRay Fab and mask identifier Temperature range Package identifier Operating frequency Tape and reel status Temperature range M = -40 C to 125 C V = -40 C to 105 C Package identifier LQ = 144 LQFP MM = 257 MAPBGA Operating frequency 1 = 120 MHz 8 = 80 MHz Tape and reel status R = Tape and reel (blank) = Trays Qualification status P = Pre-qualification M = Fully spec. qualified, general market flow S = Fully spec. qualified, automotive flow
R
Note: Not all options are available on all devices. See Table 38.
Figure 42. Commercial product code structure Table 38. Orderable part number summary
Part number1 PPC5643LFF0MLQ1 PPC5643LFF0MMM1 PPC5643LF0MLQ1 PPC5643LF0MMM1 PPC5643LFF0VLQ1 PPC5643LFF0VMM1 PPC5643LF0VLQ1 PPC5643LF0VMM1 PPC5643LFF0MLQ8 PPC5643LFF0MMM8 Flash/SRAM 1 MB/128 KB 1 MB/128 KB 1 MB/128 KB 1 MB/128 KB 1 MB/128 KB 1 MB/128 KB 1 MB/128 KB 1 MB/128 KB 1 MB/128 KB 1 MB/128 KB Package 144 LQFP (Pb free) 257 MAPBGA (Pb free) 144 LQFP (Pb free) 257 MAPBGA (Pb free) 144 LQFP (Pb free) 257 MAPBGA (Pb free) 144 LQFP (Pb free) 257 MAPBGA (Pb free) 144 LQFP (Pb free) 257 MAPBGA (Pb free) Speed (MHz)2 120 120 120 120 120 120 120 120 80 80 Other features FlexRay -40-125 C FlexRay -40-125 C No FlexRay -40-125 C No FlexRay -40-125 C FlexRay -40-105 C FlexRay -40-105 C No FlexRay -40-105 C No FlexRay -40-105 C FlexRay -40-125 C FlexRay -40-125 C
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 117
Document revision history
Table 38. Orderable part number summary (continued)
Part number1 PPC5643LF0MLQ8 PPC5643LF0MMM8 PPC5643LFF0VLQ8 PPC5643LFF0VMM8 PPC5643LF0VLQ8 PPC5643LF0VMM8
1
Flash/SRAM 1 MB/128 KB 1 MB/128 KB 1 MB/128 KB 1 MB/128 KB 1 MB/128 KB 1 MB/128 KB
Package 144 LQFP (Pb free) 257 MAPBGA (Pb free) 144 LQFP (Pb free) 257 MAPBGA (Pb free) 144 LQFP (Pb free) 257 MAPBGA (Pb free)
Speed (MHz)2 80 80 80 80 80 80
Other features No FlexRay -40-125 C No FlexRay -40-125 C FlexRay -40-105 C FlexRay -40-105 C No FlexRay -40-105 C No FlexRay -40-105 C
All packaged devices are PPC, rather than MPC or SPC, until product qualifications are complete. The unpackaged device prefix is PCC, rather than SCC, until product qualification is complete. Not all configurations are available in the PPC parts. 2 This speed rating does not include the 2% for frequency modulation.
6
Document revision history
Table 39. Revision history
Revision 1 2 Date 2 Mar 2009 5 May 2009 Initial release. Updated, Advance Information. --Revised SINAD/SNR specifications. -- Updated pinout and pin multiplexing information. Updated, Advance Information, Public release. -- Throughout this document, added information for 257 MAPBGA package. -- Updated Table 1, MPC5643L device summary. -- Updated Section 1.3, Feature Details. -- Updated pin-out and pin multiplexing tables. -- In Section 3, Electrical characteristics, added symbols for signal characterization methods. -- In Table 8, updated maximum ratings. -- In Table 10 and Table 11, removed moving-air thermal characteristics. -- Updated Section 3.8, Voltage regulator electrical characteristics. -- Updated Section 3.14, ADC electrical characteristics. -- Updated Section 3.15, Flash memory electrical characteristics. -- Updated Section 3.17.1, RESET pin characteristics. -- Removed External interrupt timing (IRQ pin) timing specifications. -- Updated Section 3.17.6, DSPI timing. -- Updated Section 5, Ordering information. Description of Changes
Table 39 summarizes revisions to this document.
3
5 Oct 2009
MPC5643L Microcontroller Data Sheet, Rev. 6 118 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Document revision history
Table 39. Revision history (continued)
Revision 4 Date 2 Mar 2010 Description of Changes Editorial changes and improvements. Revised the 257-pin package pin pitch (was 1.4 mm, is 0.8 mm). In the Overview section: * Renamed the peripheral bridge to "PBRIDGE". * Revised the information for FlexRay. * Revised the "Clock, reset, power, mode and test control module" section. * Revised the "Platform memory access time summary" table and replaced TBDs by meaningful values. Extensive revisions to signal descriptions and pin muxing information. In the "Recommended operating conditions (3.3 V)" table, changed the specification for VDD_HV_ADR0 and VDD_HV_ADR1 (was "...3.3 V", is "...3.6 V"). Revised the "EMI testing specifications" table. In the "HPREG1, HPREG2, Main LVDs, Digital HVD, and Digital LVD electrical specifications" table, added a specification for the digital low voltage detector upper threshold. Revised the "FMPLL electrical characteristics" table. In the "Main oscillator electrical characteristics" table, changed the maximum specification for gmXOSCHS (was 11 mA/V, is 11.8 mA/V). Revised the "ADC electrical characteristics" section. In the "ADC conversion characteristics" table: * Changed the tADC_S specification (was TBD, is minimum of 383 ns). * Added the footnote "No missing codes" to the DNL specification. * Added specifications for SNR, THD, SINAD, and ENOB. Revised the "Ordering information" section.
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 119
Document revision history
Table 39. Revision history (continued)
Revision 5 Date Description of Changes
31 Aug 2010 Editorial changes and improvements. Revised the Overview section. Replaced references to PowerPC with references to Power Architecture. In the feature summary, changed "As much as 128 KB on-chip SRAM" to "128 KB on-chip SRAM". In the "Feature details" section: * In the "On-chip SRAM with ECC" section, added information about required RAM wait states. * In the PIT section, deleted "32-bit counter for real time interrupt, clocked from main external oscillator" (not supported on this device). * In the flash-memory section, changed "16 KB Test" to "16 KB test sector", revised the wait state information, and deleted the associated Review_Q&A content. * In the SRAM section, revised the wait state information. In the 144-pin pinout diagram: * Renamed pin 58 (was VDD_HV_ADV0_ADV1, is VDD_HV_ADV). * Renamed pin 59 (was VSS_HV_ADV0_ADV1, is VSS_HV_ADV). In the "144 LQFP pin function summary" table, for pin 39, changed VSS_LV_COR to VDD_LV_COR. In the "Supply pins" table: * Changed the description for VDD_LV_COR (was "Voltage regulator supply voltage", is "Core logic supply"). * Changed the description for VDD_HV_PMU (was "Core regulator supply", is "Voltage regulator supply"). In the "Pin muxing" table: * In the "Pad speed" column headings, changed "SRC = 0" to "SRC = 1" and "SRC = 1" to "SRC = 0" * For port B[6], changed the pad speed for SRC=0 (was M, is F). In the "Thermal characteristics" section, added meaningful values to the thermal-characteristics tables. Added the "SWG electrical specifications" section. In the "Voltage regulator electrical characteristics" section, changed the table title (was "HPREG1, HPREG2, Main LVDs, Digital HVD, and Digital LVD electrical specifications", is "Voltage regulator electrical characteristics") and revised the table. In the "BCP68 board schematic example" figure, removed the resistor at the base of the BCP68 transistor. In the "DC electrical characteristics" table: * Changed the guarantee parameter for IINJ (was P, is T). * Added a specification for input leakage current for shared ADC input-only ports. Revised the "Flash memory module life" table. In the "FMPLL electrical characteristics" table, revised the footnote defining fSCM and fVCO. In the "Main oscillator electrical characteristics" table: * Changed the max specification for gmXOSCHS (was 11.8 mA/V, is 13.25 mA/V). * Revised the conditions for TXOSCHSSU. In the `RC oscillator electrical characteristics" table, deleted the specification for RCMTRIM. Revised the "ADC conversion characteristics" table. 31 Aug 2010 In the "RESET pin characteristics" section, changed "nRSTIN" to "RESET". (cont.) Added the "Reset sequence" section. Revised the footnotes in the "Nexus debug port timing" table. In the "Orderable part number summary" table, added a footnote about frequency modulation to the "Speed (MHz)" column heading.
5 (cont.)
MPC5643L Microcontroller Data Sheet, Rev. 6 120 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Document revision history
Table 39. Revision history (continued)
Revision 6 Date Description of Changes
11 Mar 2011 Editorial changes. In the "Document overview" section, added information about how content specific to silicon versions ("cut1" and "cut2") is presented. In the isometric miniature package drawings on the front page, removed the third dimension. Changed Symbol from P to D for "Conversion Time" in "ADC conversion characteristics" table. Added classification symbol "D" to seven entries in "Voltage regulator electrical specifications" table. Removed irrelevant Flexcan specs. Updated Table "Voltage Thresholds" to reference values specified in Table "Voltage Regulator Electrical Specifications". RDY pin added for cut2. In the "System pins" table, added a footnote about the MDO0 pad speed. Updated Rsw1 values. Added TUE-related spec information for single and double ADC channels. Added AC Test Timing Conditions to the "AC timing characteristics" section. Added a statement on the first page describing cut1 versus cut2. Moved the first paragraph from the "Description" section to the beginning of the "Document overview" section. Changed pad speed from "M" to "SYM" for FlexRay pins in the "Pin Muxing" table and added this pad type to the footnote. Moved the newly added device current specification entries from the "DC electrical characteristics" table into a newly created "Supply current characteristics" table. Added symbol "CC" to the description in the "Introduction" section. Updated "Input leakage current" specs in the "DC electrical characteristics" table. Changed TADC_S to Tsample and TADC_C toTconv in the "ADC conversion characteristics" table and footnotes. Removed "IINJ" from the "ADC conversion characteristics" table as this is included in IS1WIKNJ and IS1WWiNJ. Changed RESET_B to RESET in the "Reset sequence" section. Added the "Flash memory timing" table. Added cut2 specs for TDRB and TERLB to the "Reset sequences" table.
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 121
Document revision history
Table 39. Revision history (continued)
Revision 6 (cont.) Date Description of Changes
11 Mar 2011 Added "WKUP/NMI Timing" subsection and "WKUP/NMI Glitch Filter" table to the "AC (cont.) timing characteristics" section. Added "Nexus DDR Mode output timing" table to the "Nexus timing" section. Removed the "CLKOUT" diagram from the "External interrupt timing (IRQ pin)" section as it is not relevant. Corrected an error in the IRQ timing in the "External interrupt timing" figure. Updated the tSDC parameters in the "DSPI timing" table. Renamed the "Electromagnetic Interference (EMI) characteristics" section (is "Electromagnetic Interference (EMI) characteristics (cut1)") and revised all information in that section. In the "Voltage regulator electrical characteristics" section, added the BCX68 from Infineon to the list of supported transistors. Revised the "Voltage regulator electrical specifications" table to include cut1 and cut2 information. Renamed the "Supply current characteristics" section (is "Supply current characteristics (cut2)") and revised it to show meaningful data. In the footnotes of the "Main oscillator electrical characteristics" table, changed SELMARGIN to XOSC_MARGIN. In the "ADC conversion characteristics" table: * Changed "LSB" to "Counts". * Created separate rows for the TUE specifications. Added bullet regarding HALT and STOP in the "Clock, reset, power, mode and test control modules (MC_CGM, MC_RGM, MC_PCU, and MC_ME)" subsection of the "Features" section. In the "Analog-to-Digital Converter module" subsection of the "Feature Details" section, changed "Motor control mode" to "CTU mode" to be consistent with the nomenclature used in the Reference Manual. Updated the JCOMP entries in the "Pin function summary" table. Added footnotes regarding pad pull devices to NMI, TMS, TCK, and JCOMP in the "System pins" table. Added "Time constant of RC filter at LVD input" parameters to the "Main supply LVD (LVD Main) specifications" table. In the "Supply current characteristics (cut2)" table: * Changed "IDD_LV_MAX" to "IDD_LV_MAX"; * Removed all "40-120 MHz" frequency ranges from the "Conditions" column; * Updated the "Max" values column; * Added parameter "IDD_LV_TYP + IDD_LV_PLL" with "P" classification and special footnote; * Changed all "25C" temperature conditions to "ambient"; * Added "TJ = 150 C" condition to parameters IDD_HV_ADC, IDD_HV_AREF., IDD_HV_OSC, and IDD_HV_FLASH. Changed the timing diagram in the "Main oscillator electrical characteristics" section to reference MTRANS assertion instead of VDDMIN. Updated the jitter specs in the "FMPLL electrical characteristics" table. In the "ADC conversion characteristics" table, changed all parameters with units of "counts" to units of "LSB" and updated Min/Max values. Changed IDD_LV_BIST + IDD_LV_PLL operating current (for both cases) to TBD. In the "Supply current characteristics (cut2)" section, added a footnote that IDD_HV_ADC and IDD_HV_AREF represent the total current of both ADCs in the "Current consumption characteristics" table.
MPC5643L Microcontroller Data Sheet, Rev. 6 122 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Document revision history
Table 39. Revision history (continued)
Revision 6 (cont.) Date Description of Changes
11 Mar 2011 In the "ADC conversion characteristics" table: (cont.) * Changed DNL min from -2 to -1. * Changed OFS min from -2 to -6. * Changed OFS max from 2 to 6. * Changed GNE min from -2 to -6. * Changed GNE max from 2 to 6. * Changed SNR min from 69 to 67. * Changed TUE min (without current injection) from -6 to -8. * Changed TUE max (without current injection) from 6 to 8. * Changed TUE min (with current injection) from -8 to -10. * Changed TUE max (with current injection) from 8 to 10.
MPC5643L Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 123
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